PRELIMINARY
PRODUCT OVERVIEW
S3C6400 RISC MICROPROCESSOR
1-24
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Signal
I/O
Description
Xm1CKE[1:0]
O
Memory port 1 DRAM Clock Enable
Xm1SCLK
O
Memory port 1 DRAM Clock
Xm1SCLKn
O
Memory port 1 DRAM Inverted Clock of Xm1SCLK
Xm1CSn[1:0]
O
Memory port 1 DRAM Chip Select support up to 2 memory bank.
Xm1ADDR[15:0]
O
Memory port 1 DRAM Address bus
Xm1RASn
O
Memory port 1 DRAM Row Address Strobe
Xm1CASn
O
Memory port 1 DRAM Column Address Strobe
Xm1WEn
O
Memory port 1 DRAM Write Enable
Xm1DATA[15:0]
IO Memory port 1 DRAM Lower Half Data bus.
Xm1DATA[31:16]
IO Xm0ADDR[26:16] of SROMC.
Xm1DATA[31:16] can be used as Memory port 1 DRAM Upper Half Data bus by
System Controller setting.
Xm1DQM[3:0]
O
Memory port 1 DRAM Data Mask
Xm1DQS[3:0]
IO Memory port 1 DRAM Data Strobe
1.1.18.2 Serial Communication
•
UART / IrDA / CF
I/O
Function
Signal
0 1 2 3 4
5
6
0
1
2
3
4
5
6
XuRXD[0]
I IO I XuRXD[0]
GPA[0]
EINT1[0]
XuTXD[0]
O
IO I XuTXD[0]
GPA[1]
EINT1[1]
XuCTSn[0]
I O IO I
XuCTSn[0]
ADDR_CF[0]
GPA[2]
EINT1[2]
XuRTSn[0]
O O IO I
XuRTSn[0]
ADDR_CF[1]
GPA[3]
EINT1[3]
XuRXD[1]
I IO I
XuRXD[1]
GPA[4]
EINT1[4]
XuTXD[1]
O
IO I
XuTXD[1]
GPA[5]
EINT1[5]
XuCTSn[1]
I O IO I
XuCTSn[1]
ADDR_CF[0]
GPA[6]
EINT1[6]
XuRTSn[1]
O O IO I
XuRTSn[1]
ADDR_CF[1]
GPA[7]
EINT1[7]
XuRXD[2]
I I I O IO I
XuRXD[2]
XirRXD
ADDR_CF[0]
GPB[0]
EINT1[8]
XuTXD[2]
O O O O IO I
XuTXD[2]
XirTXD
ADDR_CF[1]
GPB[1]
EINT1[9]
XuRXD[3]
I I I O IO I
XuRXD[3]
XirRXD
ADDR_CF[2]
GPB[2]
EINT1[10]
XuTXD[3]
O O O O IO I XuTXD[3]
XirTXD
GPB[3]
EINT1[11]
XirSDBW
O IO I XirSDBW
GPB[4]
EINT1[12]