Rohm LAPIS SEMICONDUCTOR ML620Q503, Руководство пользователя

Страница: 83 / 553

ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–13
5.2.6 Interrupt Request Register 01 (IRQ01)
Address: 0F018H
Access: R/W
Access size: 8/16 bit
Initial value: 0000H
7 6 5 4 3 2 1 0
IRQ0 – – – – – – – QWDT
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
IRQ1 QEXI7 QEXI6 QEXI5 QEXI4 QEXI3 QEXI2 QEXI1 QEXI0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
IRQ01 is a special function register (SFR) used to request an interrupt for each interrupt source.
The watchdog timer interrupt (WDTINT) is a non-maskable interrupt that does not depend on MIE. In this case,
an interrupt is requested to the CPU regardless of the value of the Mask Interrupt Enable flag (MIE).
Each IRQ0 request flag is set to "1" regardless of the MIE value when an interrupt is generated.
Each IRQ1 request flag is set to "1" regardless of the IE1 and MIE values when an interrupt is generated. In this
case, an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE1) is set to "1"
and the master interrupt enable flag (MIE) is set to "1".
By setting the IRQ01 request flag to "1" by software, an interrupt can be generated.
The corresponding flag of IRQ01 is set to "0" by hardware when the interrupt request is accepted by the CPU.
Description of Bits
•
QWDT (bit 0)
QWDT is the request flag for the watchdog timer interrupt (WDTINT).
QWDT Description
0 No request (initial value)
1 Request
[Note]
When an interrupt is generated by the write instruction to the interrupt request register (IRQ0), the
interrupt shift cycle starts after the next 1 instruction is executed.
•
QEXI0 (bit 8)
QEXI0 is the request flag for the external interrupt 0 (EXI0INT).
QEXI0 Description
0 No request (initial value)
1 Request