ML620Q503/Q504 User's Manual
Chapter 15 I
2
C Bus Interface
FEUL620Q504 15–8
15.2.6 I
2
C Bus n Mode Register (I2CnMOD : n=0,1)
Address: 0F748H(I2C0MODL/I2C0MOD), 0F749H(I2C0MODH),
0F758H(I2C1MODL/I2C1MOD), 0F759H(I2C1MODH)
Access: R/W
Access size: 8/16 bits
Initial value: 0200H
7
6
5
4
3
2
1
0
I2CnMODL
–
–
–
–
I2nDW1
I2nDW0
I2nMD
I2nEN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
I2CnMODH
–
–
–
–
–
–
I2nCD1
I2nCD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
1
0
*) I2CnMODH can always read “00H” at the time of I2CnEN=0
I2CnMOD is a special function register (SFR) used to set the operation mode.
Description of Bits
•
I2nEN
(bit 0)
The I2nEN bit is used to enable the operation of the I
2
C bus interface. Only when I2nEN is “1”, the
I2nST bit can be set and the I2Cn bus becomes available. When I2nEN is set to “0”, all the SFRs related
to I
2
C bus n (I2CnMODH register is excluded) are initialized.
I2nEN
Description
0
Stops I
2
C operation (initial value)
1
Enables I
2
C operation
[Note]
Setting ports should be completed before setting I2nEN to “1”.
•
I2nMD
(bit 1)
The I2nMD bit is used to set the communication speed of the I
2
C bus interface. Standard mode or fast
mode can be selected. The communication speed varies depending on the setting value of the SYSC2,
SYSC1, and SYSC0 bits of the frequency control register (FCON0). For details, see “Table 15-1
Relationship between OSCLK and Communication Speeds”.
I2nMD
Description
0
Standard mode (initial value)/100 kbps
1
Fast mode/400 kbps
[Note]
This is set so that the communication speed becomes 100kbps/400kbps when the operating frequency
of I
2
C is 4MHz. Set the operating frequency of I
2
C in I2nCD0 and I2nCD1.
Содержание LAPIS SEMICONDUCTOR ML620Q503
Страница 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Страница 18: ...Chapter 1 Overview...
Страница 32: ...Chapter 2 CPU and Memory Space...
Страница 44: ...Chapter 3 Reset Function...
Страница 50: ...Chapter 4 Power Management...
Страница 70: ...Chapter 5 Interrupts...
Страница 134: ...Chapter 6 Clock Generation Circuit...
Страница 161: ...Chapter 7 Time Base Counter...
Страница 170: ...Chapter 8 Timers...
Страница 183: ...Chapter 9 Function Timer FTM...
Страница 231: ...Chapter 10 Watchdog Timer...
Страница 239: ...Chapter 11 Synchronous Serial Port SSIO...
Страница 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Страница 283: ...Chapter 13 UART...
Страница 303: ...Chapter 14 UART with FIFO UARTF...
Страница 327: ...Chapter 15 I2 C Bus Interface...
Страница 344: ...Chapter 16 Port XT...
Страница 350: ...Chapter 17 Port 0...
Страница 361: ...Chapter 18 Port 1...
Страница 368: ...Chapter 19 Port2...
Страница 379: ...Chapter 20 Port 3...
Страница 395: ...Chapter 21 Port 4...
Страница 410: ...Chapter 22 Port 5...
Страница 426: ...Chapter 23 Melody Driver...
Страница 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Страница 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Страница 479: ...Chapter 26 Analog Comparator...
Страница 489: ...Chapter 27 Flash Memory Control...
Страница 505: ...Chapter 28 Voltage Level Supervisor VLS...
Страница 517: ...Chapter 29 LLD circuit...
Страница 519: ...Chapter 30 On Chip Debug Function...
Страница 522: ...Appendixes...
Страница 552: ...Revision History...