Rohm LAPIS SEMICONDUCTOR ML620Q503, Руководство пользователя

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ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–37
5.2.17 Interrupt Level Control Register 6 (ILC6)
Address: 0F02EH
Access: R/W
Access size: 8/16 bits
Initial value: 0000H
7 6 5 4 3 2 1 0
ILC6L L1FTM3 L0FTM3 L1FTM2 L0FTM2 L1FTM1 L0FTM1 L1FTM0 L0FTM0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
ILC6H – – – – – – – –
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
The interrupt level control register 6 is a special function register (SFR) used to set the level of the interrupt
source enabled by IE6.
Write access to this register is possible only when the interrupt level control is enabled by the ILEN register.
Level 1 to 4 can be set for each interrupt source. The register which has the higher level is given the higher
priority.
Description of Bits
•
L1-0FTM0 (bits 1 to 0)
L1-0FTM0 set the level of the 16-bit timer 0 interrupt (FTM0INT).
L1FTM0 L0FTM0 Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4
•
L1-0FTM1 (bits 3 to 2)
L1-0FTM1 set the level of the 16-bit timer 1 interrupt (FTM1INT).
L1FTM1 L0FTM1 Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4
•
L1-0FTM2 (bits 5 to 4)
L1-0FTM2 set the level of the 16-bit timer 2 interrupt (FTM2INT).
L1FTM2 L0FTM2 Description
0 0 Level 1 (initial value)
0 1 Level 2
1 0 Level 3
1 1 Level 4