Rohm LAPIS SEMICONDUCTOR ML620Q503, Руководство пользователя

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ML620Q503/Q504 User’s Manual
Chapter 10 Watchdog Timer
FEUL620Q504 10–6
Figure 10-2 shows an example of watchdog timer operation.
Figure 10-2 Example of Watchdog Timer Operation

The WDT counter starts counting after the system reset has been released and the low-speed clock oscillation start.

The overflow period of the WDT counter (T
WOV
) is set to WDTMOD.

Write “5AH” to WDTCON. (Internal pointer 0
→
1)

Write “0A5H” to WDTCON and clear the WDT counter. (Internal pointer 1
→
0)

Write “5AH” to WDTCON. (Internal pointer 0
→
1)

If abnormalities occur and the writing of “0A5H” is not performed, WDT counter overflows. Watchdog timer
interrupt occurs because the overflow is the first overflow after reset of WDT counter. In addition, during the period
of the half clock of LSCLK, WDT counter and internal pointer are initialized. While it is initialized, the writing to
WDTCON becomes invalid, and internal pointer doesn’t turn over.

If the WDT counter is not cleared even by the software processing performed following a watchdog timer interrupt
and the WDT counter overflows again, WDT reset occurs and the mode is shifted to a system reset mode.
[Note]
•
In STOP mode, the watchdog timer operation also stops. When the WDT interrupt occurs, the HALT(DEEP-HALT,
HALT-H, HALT) mode is released.
•
The watchdog timer cannot detect all the abnormal operations. Even if the CPU loses control, the watchdog timer
cannot detect the abnormality in the operation state in which the WDT counter is cleared.

5A

A5

5A
Occurrence of
abnormality
T
WOV
Overflow period
Overflow
Low-speed
oscillation start
①
Program
start
5A A5
Data:
RESET_N
System reset
WDTCON Write
WDTP
Internal pointer
WDT counter
WDTINT
WDT interrupt
WDT reset
T
WOV
Overflow period

WDTMOD
setting
WDTMOD
setting
⑥
Occurrence of
WDTINT
⑦
Occurrence of
WDT reset