ML620Q503/Q504 User's Manual
Chapter 13 UART
FEUL620Q504
13–3
13.2.2
UART0 Receive Buffer (UA0BUF)
Address: 0F710H
Access: R/W
Access size: 8 bits
Initial value: 00H
7
6
5
4
3
2
1
0
UA0BUF
U0B7
U0B6
U0B5
U0B4
U0B3
U0B2
U0B1
U0B0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
UA0BUF is a special function register (SFR) used to store the received data.
Since data received at termination of reception is stored in UA0BUF, read the contents of UA0BUF using the
UART0 interrupt at termination of reception. At continuous reception, UA0BUF is updated whenever reception
terminates. Any write to UA0BUF is disabled.
When the 5- to 7-bit data length is selected, unnecessary bits become "0".
13.2.3
UART0 Transmit Buffer (UA1BUF)
Address: 0F718H
Access: R/W
Access size: 8 bits
Initial value: 00H
7
6
5
4
3
2
1
0
UA1BUF
U1B7
U1B6
U1B5
U1B4
U1B3
U1B2
U1B1
U1B0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
UA1BUF is a special function register (SFR) used to store the transmitted data.
Write data to be transmitted in the UA1BUF. To transmit data consecutively, confirm the U1FUL flag of the
transmit status register (UA1STAT) becomes "0", then write the next transmitted data to UA1BUF. Any value
written to UA1BUF can be read. When the 5- to 7-bit data length is selected, unnecessary bits become invalid in
the transmit mode.
Содержание LAPIS SEMICONDUCTOR ML620Q503
Страница 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Страница 18: ...Chapter 1 Overview...
Страница 32: ...Chapter 2 CPU and Memory Space...
Страница 44: ...Chapter 3 Reset Function...
Страница 50: ...Chapter 4 Power Management...
Страница 70: ...Chapter 5 Interrupts...
Страница 134: ...Chapter 6 Clock Generation Circuit...
Страница 161: ...Chapter 7 Time Base Counter...
Страница 170: ...Chapter 8 Timers...
Страница 183: ...Chapter 9 Function Timer FTM...
Страница 231: ...Chapter 10 Watchdog Timer...
Страница 239: ...Chapter 11 Synchronous Serial Port SSIO...
Страница 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Страница 283: ...Chapter 13 UART...
Страница 303: ...Chapter 14 UART with FIFO UARTF...
Страница 327: ...Chapter 15 I2 C Bus Interface...
Страница 344: ...Chapter 16 Port XT...
Страница 350: ...Chapter 17 Port 0...
Страница 361: ...Chapter 18 Port 1...
Страница 368: ...Chapter 19 Port2...
Страница 379: ...Chapter 20 Port 3...
Страница 395: ...Chapter 21 Port 4...
Страница 410: ...Chapter 22 Port 5...
Страница 426: ...Chapter 23 Melody Driver...
Страница 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Страница 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Страница 479: ...Chapter 26 Analog Comparator...
Страница 489: ...Chapter 27 Flash Memory Control...
Страница 505: ...Chapter 28 Voltage Level Supervisor VLS...
Страница 517: ...Chapter 29 LLD circuit...
Страница 519: ...Chapter 30 On Chip Debug Function...
Страница 522: ...Appendixes...
Страница 552: ...Revision History...