ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-1
14 UART with FIFO (UARTF)
14.1 General Description
The UART with FIFO (UARTF) functions as the input/output interface, carries out serial-to-parallel conversion
of the data sent from the peripheral devices, and also converts the parallel data sent from the CPU into serial data.
The UARTF has a 4-byte FIFO for transmission and reception, capable of storing up to 4 bytes of data during
transmission/reception in the FIFO mode.
Further, the receive FIFO generates 3 bits of error data for every byte of received data. The CPU can read out the
UARTF state at any time. The information that can be read out consists of the type and status of the transfer
operation under execution, and the statuses of errors such as parity, overrun, framing errors, and break interrupt,
etc.
The I/O pins of the UARTF are assigned as the tertiary function of the ports 2, 3, 4, and 5. For the ports 2, 3, 4,
and 5, see Chapter 19 "Port 2", Chapter 20 "Port 3", Chapter 21 "Port 4", and Chapter 22 "Port 5".
14.1.1 Features
•
Full duplex buffer system
•
All status reporting function
•
4-byte transmit and receive FIFOs
•
Independent control of transmit, receive, line status data set interrupt and FIFO
•
Programmable serial interface
–
5-, 6-, 7-, and 8-bit characters
–
Odd parity, even parity, no parity generation and verification
–
1, 1.5, or 2 stop bits
•
Communication speed: Settable within the range of 2400bps to 115200bps.
•
Built-in baud rate generator.
Содержание LAPIS SEMICONDUCTOR ML620Q503
Страница 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Страница 18: ...Chapter 1 Overview...
Страница 32: ...Chapter 2 CPU and Memory Space...
Страница 44: ...Chapter 3 Reset Function...
Страница 50: ...Chapter 4 Power Management...
Страница 70: ...Chapter 5 Interrupts...
Страница 134: ...Chapter 6 Clock Generation Circuit...
Страница 161: ...Chapter 7 Time Base Counter...
Страница 170: ...Chapter 8 Timers...
Страница 183: ...Chapter 9 Function Timer FTM...
Страница 231: ...Chapter 10 Watchdog Timer...
Страница 239: ...Chapter 11 Synchronous Serial Port SSIO...
Страница 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Страница 283: ...Chapter 13 UART...
Страница 303: ...Chapter 14 UART with FIFO UARTF...
Страница 327: ...Chapter 15 I2 C Bus Interface...
Страница 344: ...Chapter 16 Port XT...
Страница 350: ...Chapter 17 Port 0...
Страница 361: ...Chapter 18 Port 1...
Страница 368: ...Chapter 19 Port2...
Страница 379: ...Chapter 20 Port 3...
Страница 395: ...Chapter 21 Port 4...
Страница 410: ...Chapter 22 Port 5...
Страница 426: ...Chapter 23 Melody Driver...
Страница 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Страница 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Страница 479: ...Chapter 26 Analog Comparator...
Страница 489: ...Chapter 27 Flash Memory Control...
Страница 505: ...Chapter 28 Voltage Level Supervisor VLS...
Страница 517: ...Chapter 29 LLD circuit...
Страница 519: ...Chapter 30 On Chip Debug Function...
Страница 522: ...Appendixes...
Страница 552: ...Revision History...