Rohm LAPIS SEMICONDUCTOR ML620Q503, Руководство пользователя

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ML620Q503/Q504 User's Manual
Chapter 9 Function Timer(FTM)
FEUL620Q504 9–24
9.2.14 FTMn Interrupt Status Register (FTnINTS : n=0,1,2,3)
Address: 0F41AH(FT0INTSL/FT0INTS), 0F41BH(FT0INTSH),
0F43AH(FT1INTSL/FT1INTS), 0F43BH(FT1INTSH),
0F45AH(FT2INTSL/FT2INTS), 0F45BH(FT2INTSH),
0F47AH(FT3INTSL/FT3INTS), 0F47BH(FT3INTSH)
Access: R
Access size: 8/16 bit
Initial value: 0000H
7 6 5 4 3 2 1 0
FTnINTSL – – FTnISES FTnISTR FTnISTS FTnISB FTnISA FTnISP
R/W R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
FTnINTSH – – – – – – – –
R/W R R R R R R R R
Initial value 0 0 0 0 0 0 0 0
FTnINTS is a special function register (SFR) used to indicate the interrupt status of FTMn.
FTnINTS is a read-only register. Writing to it has no effect.
Description of Bits
•
FTnISP (bit 0)
Indicates the period interrupt state of FTMn.
FTnMD FTnISP Description
TIMER
CAPTURE
PWM1/2
0 Period interrupt has not occurred (initial value)
1
Period interrupt has occurred
This bit is cleared when writing 1 to FTnICP
•
FTnISA (bit 1)
Indicates the state of event timing A interrupt of FTMn.
Indicates that the captured data is stored to FTnEA in the CAPTURE mode.
FTnMD FTnISA Description
TIMER
PWM1/2
0 Event timing A interrupt has not occurred (initial value)
1
Event timing A interrupt has occurred
This bit is cleared when writing 1 to FTnICA
CAPTURE 0 Capture A interrupt has not occurred
1
Capture A interrupt has occurred
This bit is cleared when writing 1 to FTnICA or reading FTnEA