ML620Q503/Q504 User's Manual
Chapter 9 Function Timer(FTM)
FEUL620Q504 9–9
9.2.4 FTMn Event Register B (FTnEB : n=0,1,2,3)
Address: 0F404H(FT0EB), 0F424H(FT1EB), 0F444H(FT2EB), 0F464H(FT3EB)
Access: R/W
Access size: 16 bits
Initial value: 0000H
7
6
5
4
3
2
1
0
-
FTnEB7
FTnEB6
FTnEB5
FTnEB4
FTnEB3
FTnEB2
FTnEB1
FTnEB0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
-
FTnEB15
FTnEB14
FTnEB13
FTnEB12
FTnEB11
FTnEB10
FTnEB9
FTnEB8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
FTnEB is a special function register (SFR) used to set the event timing of FTMn or indicate the captured data.
Set this register after setting the operation mode using FTnMD.
In the CAPTURE mode, this is a read-only register. It cannot be written.
Description of Bits
•
FTnEB15-0
(bits 15 to 0)
FTnMD
FTnEB15-0
Description
TIMER
0000H-FFFFH
Set the count value to generate an interrupt. (interrupt timing is
FTnEB setting value + 1)
This value must be less than the period register FTnP.
CAPTURE
0000H-FFFFH
The captured count value is stored.
When it is read, FTnFLGB/FTnISB is cleared.
In the CAPTURE mode, writing to FTnEB is disabled.
PWM1
0000H-FFFFH
Set the duty of PWM output FTMnN of FTMn.
PWM2
*
Set FTnIEB to 0 in this mode.
Содержание LAPIS SEMICONDUCTOR ML620Q503
Страница 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Страница 18: ...Chapter 1 Overview...
Страница 32: ...Chapter 2 CPU and Memory Space...
Страница 44: ...Chapter 3 Reset Function...
Страница 50: ...Chapter 4 Power Management...
Страница 70: ...Chapter 5 Interrupts...
Страница 134: ...Chapter 6 Clock Generation Circuit...
Страница 161: ...Chapter 7 Time Base Counter...
Страница 170: ...Chapter 8 Timers...
Страница 183: ...Chapter 9 Function Timer FTM...
Страница 231: ...Chapter 10 Watchdog Timer...
Страница 239: ...Chapter 11 Synchronous Serial Port SSIO...
Страница 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Страница 283: ...Chapter 13 UART...
Страница 303: ...Chapter 14 UART with FIFO UARTF...
Страница 327: ...Chapter 15 I2 C Bus Interface...
Страница 344: ...Chapter 16 Port XT...
Страница 350: ...Chapter 17 Port 0...
Страница 361: ...Chapter 18 Port 1...
Страница 368: ...Chapter 19 Port2...
Страница 379: ...Chapter 20 Port 3...
Страница 395: ...Chapter 21 Port 4...
Страница 410: ...Chapter 22 Port 5...
Страница 426: ...Chapter 23 Melody Driver...
Страница 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Страница 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Страница 479: ...Chapter 26 Analog Comparator...
Страница 489: ...Chapter 27 Flash Memory Control...
Страница 505: ...Chapter 28 Voltage Level Supervisor VLS...
Страница 517: ...Chapter 29 LLD circuit...
Страница 519: ...Chapter 30 On Chip Debug Function...
Страница 522: ...Appendixes...
Страница 552: ...Revision History...