Rohm LAPIS SEMICONDUCTOR ML620Q503, Руководство пользователя

Страница: 252 / 553

ML620Q503/Q504 User's Manual
Chapter 12 Synchronous Serial Port with FIFO
FEUL620Q504 12–1
12 Synchronous Serial Port with FIFO (SSIOF)
12.1 General Description
The synchronous serial port with FIFO (SSIOF) can communicate with peripherals and other MCUs.
The use of SSIOF requires the function setting of the ports 2, 3, 4 and 5. For the port function setting, see
Chapter 19 "Port 2", Chapter 20 "Port 3", Chapter 21 "Port 4", and Chapter 22 "Port 5".
12.1.1 Features
•
Full-duplex data transfer
•
Master or Slave mode can be selected
•
Built-in 4-stage FIFO on each of transmit- and receive-sides
•
For the transfer size, 8 bits (byte) or 16 bits (word) can be selected
•
The number of received bytes (words) that cause interrupts can be set to 1 to 4.
•
The number of untransmitted bytes (words) that cause interrupts can be set to 0 to 3.
•
Either LSB first or MSB first can be selected
•
The polarity and phase of the serial clock are selectable
•
In Master mode, the OSCLK's 2 to 2046-division clocks can be selected as the sync clock (1023 types)
•
In Master mode, the interval before/after transfer can be controlled
•
State bit indicating transmission/receive complete and FIFO state
•
Detects a mode fault error to avoid multi-master bus contention
•
Detects a write overflow error if any further writing is attempted when the transmit FIFO is in the full state
•
Generates an interrupt when the transmit/receive FIFO is in a specific state or when a cause such as mode
fault error occurs