Rohm LAPIS SEMICONDUCTOR ML620Q503, Руководство пользователя

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ML620Q503/Q504 User's Manual
Chapter 15 I
2
C Bus Interface
FEUL620Q504 15–15
15.3.3 Operation Waveforms
Figure 15-7 shows the operation waveforms of the SDA and SCL signals. Table 15-2 shows the relationship
between communication speeds and 1/mOSCLK clock counts.
Figure 15-7 Operation Waveforms of SDA and SCL Signals
Table 15-2 Relationship between Communication Speeds and OSCLK Clock Counts
Communication
speed
(I2nSP)
Speed
reduction
(I2nDW1,0)
t
CYC
t
HD:STA
t
LOW
t
HD:DAT
t
HIGH
t
SU:STA
t
SU:DAT
t
SU:STO
t
BUF
Standard
mode
100kbps
No reduction
40φ 18φ 22φ 4φ 18φ 22φ 18φ 18φ 22φ
10% reduction
44φ 20φ 24φ 4φ 20φ 24φ 20φ 20φ 24φ
20% reduction
48φ 22φ 26φ 4φ 22φ 26φ 22φ 22φ 26φ
30% reduction
52φ 24φ 28φ 4φ 24φ 28φ 24φ 24φ 28φ
Fast
mode
400kbps
No reduction
10φ 4φ 6φ 2φ 4φ 6φ 4φ 4φ 6φ
10% reduction
11φ
4
φ 7φ 2φ 4φ 7φ 5φ 4φ 7φ
20% reduction
12φ 5φ 7φ 2φ 5φ 7φ 5φ 5φ 7φ
30% reduction
13φ 5φ 8φ 2φ 5φ 8φ 6φ 5φ 8φ
φ: Clock cycle of 1/mOSCLK
m: Depends on the setting of the I2nCD1 and I2nCD0 bits of the I2CnMOD register.
[Note]
The 1/mOSCLK clock count is set so that the communication speed may be set to 100 kbps/400kbps
when 1/mOSCLK is 4MHz.
SDA
Start
condition
Restart
condition
Stop
condition
SCL
t
HD:STA
t
LOW
t
HIGH
t
HD:DAT
t
SU:STA
t
SU:STO
t
BUF
t
SU:DAT
t
CYC