Rohm LAPIS SEMICONDUCTOR ML620Q503, Руководство пользователя

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ML620Q503/Q504 User's Manual
Chapter 6 Clock Generation Circuit
FEUL620Q504 6–13
6.3.1.3 Low-Speed External Clock Input Mode
In external low-speed clock input mode, external clock is input from the PXT1 pin. Figure 6-5 shows the circuit
configuration in the external low-speed clock input mode.
Figure 6-5 Circuit Configuration in the External Clock Input Mode
[Note]
•Since the PXT1 pin has a built-in diode to V
DD
and V
SS
, avoid applying voltages higher than the V
DD
and
lower than the V
SS
.
•If the PXT1 pin is left open in low-speed external clock input mode, excessive current can flow. Therefore,
make sure that the "H" level (V
DD
) or the "L" level (V
SS
) is input.
•For the PXT1 pin, an input clock should not exceed 36kHz.
PXT1
External clock input
V
DD
STOP mode
Low-speed oscillation
clock (LSCLK)
16 counts