ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-4
14.2.2 UARTF0 Transmit/Receive Buffer (UAF0BUF)
Address: 0F7C0H
Access: R/W
Access size: 8/16 bits
Initial value: Undefined
7
6
5
4
3
2
1
0
UAF0BUFL
UF0B7
UF0B6
UF0B5
UF0B4
UF0B3
UF0B2
UF0B1
UF0B0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
x
x
x
x
x
x
x
x
15
14
13
12
11
10
9
8
UAF0BUFH
UF0B15
UF0B14
UF0B13
UF0B12
UF0B11
UF0B10
UF0B9
UF0B8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
UAF0BUF is a special function register (SFR) that provides the following three functions.
(1)
Read-only register for buffering received data: Receiver Buffer Register (RBR)
RBR is the register that holds received data from 5 to 8 bits depending on the character length.
The bit 0 of a data word is always the first serial data bit received. If data less than 8 bits is received, the data
is entered in the right justified manner towards the LSB.
When the UART carries out parallel-to-serial or serial-to-parallel conversion operation, the register has the
double buffer configuration so that read operations can be made.
RBR can be read by program when UF0DLAB of UAF0MOD is 0. When UAF0BUF is read, RBR can be
read from UnB7-0. For UF0B15-8, 00H can be read.
The reset value is undefined.
(2)
Write-only register for setting transmitted data: Transmitter Holding Register (THR)
THR is the register that holds transmitted data from 5 to 8 bits depending on the character length.
The bit 0 of the data word is always the first serial data bit that is transmitted.
When the UART carries out parallel-to-serial or serial-to-parallel conversion operation, the register has the
double buffer configuration so that write operations can be made.
THR can be written by program when UF0DLAB of UAF0MOD is 0. When UAF0BUF is written, the
UF0B7-0 data is written to THR. The UF0B15-8 data are invalid.
(3)
16-bit divisor latch for baud rate generator: Divisor Latch Resister (DLR)
DLR can be read/written by program when UF0DLAB of UAF0MOD is 1. For details, see "Baud rate clock
generation".
UF0DLAB = 0
UF0DLAB = 1
UAF0BUF[15:8]
UAF0BUF[7:0]
UAF0BUF[15:8]
UAF0BUF[7:0]
Read
00H
RBR
DLR[15:8]
DLR[7:0]
Write
Disabled
THR
DLR[15:8]
DLR[7:0]
Содержание LAPIS SEMICONDUCTOR ML620Q503
Страница 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Страница 18: ...Chapter 1 Overview...
Страница 32: ...Chapter 2 CPU and Memory Space...
Страница 44: ...Chapter 3 Reset Function...
Страница 50: ...Chapter 4 Power Management...
Страница 70: ...Chapter 5 Interrupts...
Страница 134: ...Chapter 6 Clock Generation Circuit...
Страница 161: ...Chapter 7 Time Base Counter...
Страница 170: ...Chapter 8 Timers...
Страница 183: ...Chapter 9 Function Timer FTM...
Страница 231: ...Chapter 10 Watchdog Timer...
Страница 239: ...Chapter 11 Synchronous Serial Port SSIO...
Страница 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Страница 283: ...Chapter 13 UART...
Страница 303: ...Chapter 14 UART with FIFO UARTF...
Страница 327: ...Chapter 15 I2 C Bus Interface...
Страница 344: ...Chapter 16 Port XT...
Страница 350: ...Chapter 17 Port 0...
Страница 361: ...Chapter 18 Port 1...
Страница 368: ...Chapter 19 Port2...
Страница 379: ...Chapter 20 Port 3...
Страница 395: ...Chapter 21 Port 4...
Страница 410: ...Chapter 22 Port 5...
Страница 426: ...Chapter 23 Melody Driver...
Страница 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Страница 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Страница 479: ...Chapter 26 Analog Comparator...
Страница 489: ...Chapter 27 Flash Memory Control...
Страница 505: ...Chapter 28 Voltage Level Supervisor VLS...
Страница 517: ...Chapter 29 LLD circuit...
Страница 519: ...Chapter 30 On Chip Debug Function...
Страница 522: ...Appendixes...
Страница 552: ...Revision History...