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ML620Q503/Q504 User's Manual
Chapter 12 Synchronous Serial Port with FIFO
FEUL620Q504 12–26
12.3.10 FIFO Operation
SSIOF includes the receive FIFO of 4 words and the transmit FIFO of 4 words. The FIFO state is indicated in the
SF0TFF, SF0TFE, SF0RFF, and SF0RFE bits of SF0SRR, and the SF0TFD and SF0RFD bits of SF0FSR.
There are three FIFO states, Full (SF0TFF and SF0RFF), Empty (SF0TFE and SF0RFE), and Depth (SF0TFD
and SF0RFD).
12.3.11 Write Overflow
If further writing is performed when the transmit FIFO is in Full status (SF0TFF = 1), a write overflow is set.
(SF0WOF=1)
However, interrupt is not generated even when a write overflow occurs.
SF0WOF is cleared when SF0SRR is read.
12.3.12 Overrun Error
If further reception is performed when the receive FIFO is in Full status (SF0RFF = 1), an overrun error occurs.
(SF0ORF=1)
If an overrun error occurs, the SF0ORF bit of SF0SRR is set, and an overrun error interrupt is generated. The
newly received data is not held.
Read the content of the receive FIFO, clear the SF0RFF bit, then write "1" in the SF0ORFC bit to clear the
SF0ORF bit.
12.3.13 FIFO Clearance
If this bit is set to 1, the transmit/receive counter control of FIFO returns to the initial setting state(SF0SRR
register to SF0TFF=0, SF0TFE=1, SF0RFF=0, and SF0RFE=1, and SF0FSR register to SF0TFD=000 and
SF0RFD=000).
Valid only when SF0SPE is set to 0.
Return SF0FICL to 0 before performing a transfer.
Even if this bit is set to 1, the interrupt is not changed for SF0RFIC, SF0TFIC, SF0ORIE, SF0FIE, SF0RFIE,
and SF0TFIE of the SF0INTC register, and SF0ORF, SF0FI, SF0RFI, and SF0TFI of the SF0SRR register.
This bit can be used to discard the data of FIFO when the communication is stopped.