Rohm LAPIS SEMICONDUCTOR ML620Q503, Руководство пользователя

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ML620Q503/Q504 User's Manual
Chapter 14 UART with FIFO(UARTF)
FEUL620Q504 14-18
RXDF0 Start Data bit (5
～
8) Parity Stop
Sample CLK FIFO below Trigger Level
UAF0INT
(Received Data Available)
FIFO at or above
tSINT tRINT Trigger Level
UAF0INT
(Received Line Status)
tRINT
RD
LSR read RBR read
tSINT: MAX 3 Buad rate Clocks
tRINT: MAX 1 Baud rate Clock
Figure 14-5 First Byte of Receive FIFO (Set RBR)
RXDF0 Start Data bit (5
～
8) Parity Stop
Sample CLK FIFO below Trigger Level
UAF0INT
(Received Data Available) tSINT
tRINT FIFO at or above
Trigger Level
UAF0INT Top Byte of FIFO
(Received Line Status)
tSINT tRINT
RD
RBR read LSR read RBR read
(Previous Byte read
from FIFO) tSINT: MAX 3 Buad rate Clocks
For a timeout, 8 Baud rate Clocks
tRINT: MAX 1 Baud rate Clock
Figure 14-6 Remaining Bytes in Receive FIFO