ML620Q503/Q504 User's Manual
Chapter 5 Interrupts
FEUL620Q504 5–16
5.2.7 Interrupt Request Register 23 (IRQ23)
Address: 0F01AH
Access: R/W
Access size: 8/16 bit
Initial value: 0000H
7
6
5
4
3
2
1
0
IRQ2
–
QUAF0
QUA1
QUA0
QI2C1
QI2C0
QSIOF0
QSIO0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
IRQ3
QMD0
QVLS
QLOSC
–
–
–
–
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0
IRQ23 is a special function register (SFR) used to request an interrupt for each interrupt source.
Each IRQ23 request flag is set to "1" regardless of the IE23 and MIE values when an interrupt is generated. In
this case, an interrupt is requested to the CPU when the related flag of the interrupt enable register (IE23) is set to
"1" and the master interrupt enable flag (MIE) is set to "1".
By setting the IRQ23 request flag to "1" by software, an interrupt can be generated.
The corresponding flag of IRQ2 is set to "0" by hardware when the interrupt request is accepted by the CPU.
Description of Bits
•
QSIO0
(bit 0)
QSIO0 is the request flag for the synchronous serial port 0 interrupt (SIO0INT).
QSIO0
Description
0
No request (initial value)
1
Request
•
QSIOF0
(bit 1)
QSIOF0 is the request flag for the synchronous serial port 0 interrupt with FIFO (SIOF0INT).
QSIOF0
Description
0
No request (initial value)
1
Request
•
QI2C0
(bit 2)
QI2C0 is the request flag for the I2C bus 0 interrupt (I2C0INT).
QI2C0
Description
0
No request (initial value)
1
Request
Содержание LAPIS SEMICONDUCTOR ML620Q503
Страница 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Страница 18: ...Chapter 1 Overview...
Страница 32: ...Chapter 2 CPU and Memory Space...
Страница 44: ...Chapter 3 Reset Function...
Страница 50: ...Chapter 4 Power Management...
Страница 70: ...Chapter 5 Interrupts...
Страница 134: ...Chapter 6 Clock Generation Circuit...
Страница 161: ...Chapter 7 Time Base Counter...
Страница 170: ...Chapter 8 Timers...
Страница 183: ...Chapter 9 Function Timer FTM...
Страница 231: ...Chapter 10 Watchdog Timer...
Страница 239: ...Chapter 11 Synchronous Serial Port SSIO...
Страница 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Страница 283: ...Chapter 13 UART...
Страница 303: ...Chapter 14 UART with FIFO UARTF...
Страница 327: ...Chapter 15 I2 C Bus Interface...
Страница 344: ...Chapter 16 Port XT...
Страница 350: ...Chapter 17 Port 0...
Страница 361: ...Chapter 18 Port 1...
Страница 368: ...Chapter 19 Port2...
Страница 379: ...Chapter 20 Port 3...
Страница 395: ...Chapter 21 Port 4...
Страница 410: ...Chapter 22 Port 5...
Страница 426: ...Chapter 23 Melody Driver...
Страница 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Страница 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Страница 479: ...Chapter 26 Analog Comparator...
Страница 489: ...Chapter 27 Flash Memory Control...
Страница 505: ...Chapter 28 Voltage Level Supervisor VLS...
Страница 517: ...Chapter 29 LLD circuit...
Страница 519: ...Chapter 30 On Chip Debug Function...
Страница 522: ...Appendixes...
Страница 552: ...Revision History...