Rohm LAPIS SEMICONDUCTOR ML620Q503, Руководство пользователя

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ML620Q503/Q504 User's Manual
Chapter 24 RC Oscillation Type A/D Converter
FEUL620Q504 24-14
24.3.2 Counter A/B Reference Modes
There are the following two modes of RC-ADC conversion operation:
•
Counter A reference mode (RADMOD RADI = “0”)
In this mode, a gate time is determined by Counter A and the base clock (BSCLK), which is used as the time
reference, then the RC oscillator clock (RCCLK) is counted by Counter B within the gate time to make the
content of Counter B the A/D conversion value.
The A/D conversion value is proportional to RC oscillation frequency.
•
Counter B reference mode (RADMOD RADI = “1”)
In this mode, a gate time is determined by Counter B and the RC oscillator clock (RCCLK), and the base
clock (BSCLK), which is used as the time reference, is counted by Counter A within the gate time to make the
content of Counter A the A/D conversion value.
The A/D conversion value is inverse proportional to RC oscillation frequency.
(1)
Operation in Counter A reference mode
Figure 25-6 shows the operation timing in Counter A reference mode.
Following is an example of operation procedure in Counter A reference mode:

Preset to Counter A (RADCA0 and RADCA1) the value obtained by subtracting the count value “nA0”
from the maximum value + 1 (1000000H). The product of the count value “nA0” and the BSCLK clock
cycle indicates the gate time.
k
Preset “000000H” in Counter B (RADCB0 and RADCB1).
l
Set the OM3–OM0 bits of RADMOD to desired oscillation mode. (See Table 24-1)

Set the RADI bit of RADMOD to “0” to specify generating of an interrupt request signal by Counter A
overflow.
n
Set the RARUN bit of RADCON to “1” to start A/D conversion.
Counter A starts counting of the base clock (BSCLK) when RARUN is set to “1” and the RCON signal (signal
synchronized with the fall of the base clock) is set to “1”. When Counter A overflows, the RARUN bit is
automatically reset to “0” (

) and counting is terminated. At the same time, an RC-ADC interrupt request
(RADINT) occurs (

).
When the RCON signal is set to “1”, the RC oscillator circuit starts operation and Counter B starts counting of
the RC oscillator clock (RCCLK). When the RARUN bit is reset to “0” due to overflow of Counter A, RC
oscillation stops and Counter B stops counting.
The final count value “nB0” of Counter B is the RCCLK count value during the gate time “nA0 x t
BSCLK
” and is
expressed by the following expression:
nB0
≅
nA0•
t
BSCLK
∝
f
RCCLK
t
RCCLK
The t
BSCLK
indicates the BSCLK period and t
RCCLK
the RCCLK period. That is, “nB0” is a value proportional to
the RC oscillation frequency f
RSCLK
.