ML620Q503/Q504 User’s Manual
Chapter 3 Reset Function
FEUL620Q504 3–3
3.2.2 Reset Status Register (RSTAT)
Address: 0F00CH
Access: R/W
Access size: 8 bits
Initial value: Undefined
7
6
5
4
3
2
1
0
RSTAT
–
–
–
LLDR
VLSR
WDTR
–
POR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
x
x
x
0
x
*)The initial value depends on the reset factor
RSTAT is a special function register (SFR) that indicates the causes set to the system reset mode.
At the occurrence of reset, the contents of RSTAT are not initialized, while the bit indicating the cause of the reset is set
to ”1”. When checking the reset cause using this function, perform write operation to RSTAT in advance and initialize
the each reset cause flag of RSTAT to “0”.
Description of Bits
•
POR
(bit 0)
The POR bit is a flag that indicates that the power-on reset is generated. This bit is set to “1” when powered on.
POR
Description
0
Power-on reset not occurred
1
Power-on reset occurred
•
WDTR
(bit 2)
The WDTR is a flag that indicates that the watchdog timer reset is generated. This bit is set to “1” when the reset by
overflow of the watchdog timer is generated.
WDTR
Description
0
Watchdog timer reset not occurred
1
Watchdog timer reset occurred
•
VLSR
(bit 3)
The VLSR is a flag that indicates that the Voltage Level Supervisor reset is generated. This bit is set to “1” when the
reset by overflow of the Voltage Level Supervisor generated. Also, the bit is undifined when the power is turned on.
VLSR
Description
0
Voltage Level Supervisor reset not occurred
1
Voltage Level Supervisor reset occurred
•
LLDR
(bit 4)
The LLDR is a flag that indicates that the Low Level Detector reset is generated. This bit is set to “1” when the reset
by overflow of the Lowe Level Detector is generated. Also, the bit is undifined when the power is turned on..
LLDR
Description
0
Low Level Detector reset not occurred
1
Low Level Detector reset occurred
[Note]
No flag is provided that indicates the occurrence of reset by the RESET_N pin.
Содержание LAPIS SEMICONDUCTOR ML620Q503
Страница 2: ...ML620Q503 Q504 User s Manual Issue Date Apr 16 2015 FEUL620Q504 01...
Страница 18: ...Chapter 1 Overview...
Страница 32: ...Chapter 2 CPU and Memory Space...
Страница 44: ...Chapter 3 Reset Function...
Страница 50: ...Chapter 4 Power Management...
Страница 70: ...Chapter 5 Interrupts...
Страница 134: ...Chapter 6 Clock Generation Circuit...
Страница 161: ...Chapter 7 Time Base Counter...
Страница 170: ...Chapter 8 Timers...
Страница 183: ...Chapter 9 Function Timer FTM...
Страница 231: ...Chapter 10 Watchdog Timer...
Страница 239: ...Chapter 11 Synchronous Serial Port SSIO...
Страница 251: ...Chapter 12 Synchronous Serial Port with FIFO SSIOF...
Страница 283: ...Chapter 13 UART...
Страница 303: ...Chapter 14 UART with FIFO UARTF...
Страница 327: ...Chapter 15 I2 C Bus Interface...
Страница 344: ...Chapter 16 Port XT...
Страница 350: ...Chapter 17 Port 0...
Страница 361: ...Chapter 18 Port 1...
Страница 368: ...Chapter 19 Port2...
Страница 379: ...Chapter 20 Port 3...
Страница 395: ...Chapter 21 Port 4...
Страница 410: ...Chapter 22 Port 5...
Страница 426: ...Chapter 23 Melody Driver...
Страница 439: ...Chapter 24 RC Oscillation type A D Converter RC ADC...
Страница 462: ...Chapter 25 Successive Approximation Type A D Converter SA ADC...
Страница 479: ...Chapter 26 Analog Comparator...
Страница 489: ...Chapter 27 Flash Memory Control...
Страница 505: ...Chapter 28 Voltage Level Supervisor VLS...
Страница 517: ...Chapter 29 LLD circuit...
Страница 519: ...Chapter 30 On Chip Debug Function...
Страница 522: ...Appendixes...
Страница 552: ...Revision History...