Rohm LAPIS SEMICONDUCTOR ML620Q503, Руководство пользователя

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ML620Q503/Q504 User's Manual
Chapter 13 UART
FEUL620Q504 13–16
13.3.5 Receive Operation
Select the receive data pin using the U0RSEL bit of the UART0 mode register 0 (UA0MOD0). Reception is
started by setting the U0EN bit of the UART0 control register (UA0CON) to "1".
Figure 13-6 shows the operation timing for reception.
When receive operation starts, the LSI checks the data sent to the input pin RXD and waits for the arrival of a
start bit.
When detecting a start bit (

), the LSI generates the internal transfer clock of the baud rate set with the start bit
detect point as a reference and performs receive operation.
The shift register shifts in the data input to RXD on the rising edge of the internal transfer clock. The data and
parity bit are shifted into the shift register and 5- to 8- bit received data is transferred to the receive buffer
(UA0BUF) concurrently with the falling edge of the internal transfer clock of

.
The LSI requests a UART reception interrupt on the rising edge of the internal transfer clock subsequent to the
internal transfer clock by which the received data was fetched (

) and checks for a stop bit error and a parity bit
error. When an error is detected, the LSI sets the corresponding bit of the UART0 status register (UA0STAT) to
" 1 " .
Parity error
: U0PER ="1"
Overrun error : U0OER ="1"
Framing error : U0FER ="1"
As shown in Figure 13-6, the rise of the internal transfer clock is set so that it may fall into the middle of the bit
interval of the received data.
Reception continues until the U0EN bit is reset to "0" by the program. When the U0EN bit is reset to "0" during
reception, the received data may be destroyed. When the U0EN bit is reset to "0" during the "U0EN reset enable
period" in Figure 13-6, the received data is protected.