HP 3562A, Руководство по обслуживанию

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C I RC U I T DESC R I PT I ONS
MOD E L 3562A
6-82
CTR2 B 1 l
Cou nter two, bit 1 1 . Bit 1 1 on the FFT add ress bus (FA1 1) originates in one
of two places: cou nter two or the page register. The s ignal from the page
register is W1 1 . The sequence decoder picks one of these two, depend ing
on some other add ressing criteria, and puts out FA1 1 .
Wl l
See CTR2 B1 1 .
FAl l
See CTR2 B1 1 .
CTR1 E N L
Cou nter select, cou nte r one i s selected when low.
DEC2L
Decrement cou nter two, active low.
I N C2L
I ncrement cou nter two, active low.
I N Cl L
I ncrement cou nter one, active low.
F FTWR
FFT write. Command from the I/O sequencer to the global bus handshake
circuit to write. Also used in conjunction with the W I N DPG L signal as input
to the page register to determine address page to use depend ing on whether
the operation is a read or a write and the data is window i nformation or
coefficient information. (It is not possible to write coefficient information).
W I N D PG L
Window page, active low. Used in conjunction with FFTWR as in put to the
page register. See FFTWR.
PASSB ITO
A signal ANDed with b it 0 on the FFT add ress bus so that it passes bit 0
when high and holds bit 0 low when low. See the discussion on the add ress
translator.
G D I N EMPTY
G lobal data input reg ister empty. I ndicates that there is no data waiting
to be read from the global data bus registers.
C lREM PTYl
Clears the G D It"� EM PTY fl ip-flop.
GDO UTRDY
Ldat<L_
-
- -
C LRRDYL
F FTMR
F FTMG
POSTlNCL
Clears the G DOUTRDY flip-flop.
FFT memory req uest. This signal is active high between the time that the
FFT board req uests the global bus and the time that i,t is granted control
of the bus. It is an input to the I/O seq uencer.
FFT memory grant. This signal is a d i rect resu lt of the FFT board being
granted control of the global bus. I t is an input to the I/O sequencer.
Post increment, active low. Controls whether cou nters are incremented after
a read or write.