HP 3562A, Руководство по обслуживанию

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MOD E L 3562A
C I RC U I T DESCR I PT I ONS
Programmable Timer Module
The programmable timer module is an i nternal time base generator, clocked by the E N B L
clock from the system processor. This timer is used for function time outs an<;l to m ai ntain
relative time i ntervals. This m odule contains three clocks which get addressed by signals
A1 to A3. The clocks are loaded and read by the system processor using the C PU data
li nes DO to D7. A clock is enabled by the program timer mod u le signal PTML. When the
program timer module clock finishes cou nting, the i nterrupt request I RQT7L is generated.
Bus Time Out
When a system processor bus cycle is i n itiated, the bus time out ripple counter is started
and runs u ntil either the handshake is completed (DTAC K L or VPAL is received) or the
cou nter reaches its terminal cou nt. I f the timer reaches the term i n al cou nt of 32 p.,s
before the handshake is com pleted, the bus error l ine (BE RRL) to the system p rocessor
is asserted to abort the cu rrent bus cycle. The system processor then begins processing
for the bus error. Bus errors are entered in the fault log along with the name of the assembly
that failed to send the handshake signal.
Status Decoder
When the system processor is perfor m i ng an operation, the status decoder l ights one of
the status LEDs (DS2). The status operations and correspond i ng L E Ds are as fol lows:
LED Label
DS2-5 U D
DS2-4 U P
DS2-3 SD
SP
Description
User Data, CPU in user state and accessing data
User Program, CPU i n user state and accessing program
Supervisor Data, CPU in su pervisor state and accessing
data
SupeivisOi PiOgiam, CPU i n su pervisor state and accessing
program
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