HP 3562A, Руководство по обслуживанию

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MOD E L 3562A
G R/GWL
G RAM RST L
G SMPLL
G SW
H D1 to H D8
H IGH I N P UT 1
H IGH I N P UT
2
C I RC U I T D E SC R I PT I O N S
The global b u s consists of the fol lowing signals:
GDOL to G D1 5 L . . . . . . g lobal data bus
GA1 L to GA1 6L . . . . . . global add ress bus
G DSL . . . . . . . . . . . . . . . g lobal data strobe
G R/GWL . . . . . . . . . . . . global read/global write
Memory Request l ines MRFFTL, MRDF2 L, MRDF1 L, MR68L, and
MRFPPL.
Memory G rant l ines MG FFT, MG DF2 L, MGDF1 L, MG68L, and
MG FPPL.
G LO BAL READ/G LO BAL WRITE
Active Low
When low, this open col lector signal defines the global data bus
transfer as a write cycle. When it is high, the transfer is a read cyc le.
G LOBAL RAM R E S E T
Active Low
Signal from the A2 System C P U to the A8 G lobal RAM. When power
is app l ied to the instrument or A2 S1 is activated, G RAMRSTL goes
low and resets the global RAM. This signal is used to reset the global
RAM instead of R E S ETL, so a software reset does not reset the
A8 G lobal RAM
G LOBAL SAM P L E
Active Low
At this time, this s ignal from the A8 G lobal RAM is not used by any
assembly in the instrument.
PASS GAI N SWI TC H
(A32, A34 TP604)
This signal is used by the A32 ADC 1 and the A34 ADC 2. GSVv' is from
the ADC contro l l er to the ADC process switch. It is used with C LADC
to dete
'
.
ut to th A D C '
DATA
These l ines are the data lines between the A2 System CPU and the
A22 H P-I nterface Bus.
H IG H I N PUT 1
H I G H I N PUT 2
(A33, A35 J 300-1 )
These are the input signals from the front panel BNC centers to the
A33 . l nput 1 and A35 I nput 2 assembl ies.
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