HP 3562A, Руководство по обслуживанию

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MODE L 3562A C I RCU IT DESCR I PT I O N S
6-1 0 A9, FAST fOURIER TRANSfORM (ffTJ PROCESSOR
The Fast Fourier Transform (FFT) p rocessor board performs windowi ng, Fast Fou rier
Transform, and inverse Fast Fourier Transforms as specified by the System CPU (A2). I nput
and output data are stored in memory blocks in the global RAM.
T
he FFT board performs
the memory access (controls the global bus) to move these blocks to and from global
memory (on the global bus). I nput data may be real or com plex, for one channel or two.
The description of how the FFT works covers operation at the system level (between the
FFT board and the system CPU) and at the board level. Refer to the block d iagrams in
figu res 6-A9a and 6-A9b and the schematic in figu re 8-A9 for the fo l lowing discussion of
the theory of operation.
FFT Interaction with the CPU
The FFT board is control led by the system CPU (A2) through the system bus. The FFT board
appears to the main C P U board as a set of registers. These registers (sometimes cal led
pseudo-registers) exist as RAM i nside the FFT m icroprocessor chip.
FFT I/O is not synchronized with other activity on the global bus. The FFT requests control
of the g lobal bus for d i rect memory access (DMA) whenever it is necessary to get input
data or store output data. The FFT has the highest priority i nterrupt status in the DMA
chain. Memory access is provided with in 500 ns of the FFT memory req uest.
FFT Microprocessor System
The FFT microprocessor (U1 03) is a TMS320 runn ing at 5 M H z . The crystal osc i l l ates at
20 MHz but the TMS320 divides that by four. The TMS320 and its ROM (U301 and U303)
form a complete microprocessor system. The data bus between the TMS320 and its ROM
is connected to the FFT i ntemal data bus through a transceiver. The rest of the circu itry
on the board appears to this system as individual I/O ports. The ports are activated by
addressing combinations which activate the port decoder. The circu its that are not directly
controlled by the TMS320 through the port decoder are i nd i rectly control led through the
hardware control register.
Port Decoder
appears to�t -eTMS320 as I/O ports on the i nternal data
bus. The TMS320 enab les ports through address and control l ines which are i n put l ines
for the port decoder. When an add ress corresponding to a port appears on the address
bus and the control l ines are enabled, the port decoder selects one of thirteen l i nes to
activate. These li nes are descri bed i n the first part of the internal signal descriptions at
the end of the FFT 'circ u it description.
Hardware Control Register
The hardware control register (U405 and U406) is used to control circu its that are not directly
connected to the intern al data bus. It appears to the TMS320 as a write-only register on
the internal data bus and is activated through the port decoder. I t allows the TMS320
to control the gl obal bus I/O sequencer, contro l the type of transform done, keep track
of the level and scale factor d u ring the transform, and mon itor scale factors and execution
status.
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