HP 3562A, Руководство по обслуживанию

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MOD E L 3562A
C I RC U I T DESCR I PTIONS
6-1 4 A3 1 TRIGGER
The trigger assembly prod uces the trigger signal (TR I G RO) for the A1 Digital Sou rce and
the A5 Digital Fi lter and the sam ple signal (CONY) that is sent to the A32, A34 ADCs.
The trigger assembly also generates the 1 0.24 MHz clock used by the A1 D igital Sou rce,
the A4 Local osci llator, the A5 Digital Fi lter, the A6 Digital Fi lter Control ler, the A30 Analog
Sou rce, and the A32, A34 ADCs assembl ies. The 1 0.1 4 MHz clock can be locked to an
external reference signal by using the rear panel RE F I N i nput.
Trigger Level Circuit
(Refer to figure 6-A31 a) To prod uce the trigger level, the trigger assembly uses one of four
analog inputs; external trigger (EXT TRI G G E R), channel 1 (TRIG1 @), channel 2 (TRIG2 @ ),
or trigger calibration (CAL TRI G). The trigger select switch selects one of the input signals
and passes it to a com parator. The selected analog in put is compared to a dc voltage
from the trigger's DAC. The output of the comparator is lbw as long as the analog signal
is below this 'dc value and is high if the analog signal is above the dc val ue. The output
of the comparator is then sent through an exclusive OR gate which i nverts the signal if
the slope select l ine is high.
Trigger Control
The operations of the trigger assembly are control led through the trigger's shift reg ister.
The sh ift register sh ifts in a command word from the A1 Digital Sou rce assemb ly. The
command word sets the i nput trigger selection, the trigger level, the trigger slope, and
whether an i nternal .or external sam ple is used (SE LXS).
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