HP 3562A, Руководство по обслуживанию

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MOD E L 3562A
C I RC U IT DESCR I PT I O N S
G LOBAL ADDRESS BUS I NT E R FAC E
The'global address bus interface (U51 1 and U51 2) is a latch circ u it which exists between
the FFT address bus and the global add ress bus. These l atches are cl ocked when the FFT
board req uests contro l of the global bus and are enabled when the FFT board is granted
contro l of the bus.
G LOBA L DATA BUS I NT E RFAC E
The global data bus interface appears as one read-on ly register and one write-only register
to the TMS320. They are enabled by signals G D B I N L and GDBOUTL from the port decoder.
G LOBA L BUS HANDSHAK I N G
This block is used to coord inate data transfers between the FFT board and global RAM.
When the FFT board needs access to memory, it requests control of the global bus by
activating REQG BL (req uest global bus) signal to the handshake block. This activates the
MRFFTL (memory req uest from FFT) signal going off the FFT board. When the MG FFTL
(memory grant to the FFT) signal becomes active, the memory req uest is removed and
the read or write is performed through the global data bus i nterface. If the operation is
a read, the G DS L (global data strobe) signal is used to indicate when the data on the bus
is val id. If the operation is a write, the data is loaded i nto the write register at the same
time the G R/GWL (global read/global write) signal is set low to i ndicate to the memory
that the data on the bus is val id.
Pseudo-Scale ROM
A l l data operations are done in the TMS320 microprocessor. The only hardware doing
math operations outside the TMS320 is the pseudo-scale ROM (U305). It looks at the internal
data bus on each data write cycle and compares the upper eight bits to val ues stored
in memory. The two output l ines are rec locked by flip-flops in U208. The TMS320 clocks
them when it puts someth ing on the global data bus. The flip-flops store the largest val ue
output for that parti cular pass of the FFT. Before beginning the next pass, the TMS320
examines (and c lears) the D IVBY4 and DIVBY2 li nes (horn the flip-flops) to see how big
the data was on the last pass; it then can select a scale for the next pass.
The TMS320 keeps track of the add ress process via the Butterfly Type P LA (U207) and
the Butterfly Su broutine Add ress ROM (U502)-hereafter referred to as the Butterfly ROM.
The Butterfly ROM is a read-only po rt on the i nternal data bus which is activated by the
port decoder. The TMS320 uses information from this logic to keep track of execution
status of the transform to gu ide its math operations (help select su broutines). Depend ing
on where execution is in the pass, the TYPE2BF l i ne from U207 tel ls the ROM which of
two types of butterfly routines to execute.
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