HP 3562A, Руководство по обслуживанию

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MOD E L 3562A C I RC U I T DESC R I PTIONS
Trigger Clock Circuit
(Refer to figure 6-A31 b) The trigger clock circuit prod uces the 10.24 M H z clock using a
voltage control led crystal osc i l l ator (VCXO). When there is no external reference s ignal
(REF I N) the phase lock loop is not u sed. The error voltage into the PLL gain and shaping
subblock is zero. The freq uency adjustment is used to adjust the frequency out of the
VCXO to precisely 20.48 MHz. This signal is divided by two to form the 1 0.24 MHz clock.
The 1 0.24 MHz s ignal is divided by forty to prod uce the internal sample signal (CONV,
256 kHz). The convert mu ltiplexer selects the internal sam ple signal or an external sam­
ple s ignal. The signal S E LXS from the sh ift reg ister determines which is selected.
The phase lock loop is used when there is an external reference sign a l . The external
reference signal can be 1 ,2,5, or 1 0 M H z . The difference in freq uency between the 3.41 3
MHz harmonic of the external reference and the 3.41 3 MHz output of the VCXo are used
for the phase comparison. The sam pler subblock sam ples the 3.41 3 MHz clock from the .
VCXO with R E F I N
+
3 to prod uce the sum and difference frequencies of the clock and
the reference signal's harmon ics. These frequencies are then put through a band pass fi lter
to prod uce an 80 kHz signal.
At the same time the 80 kHz signal is being produced, the REF IN is divided by 1 25. The
phase detector samples the 80 kHz s ignal with the RE F I N
+
1 25 signal to prod uce an er­
ror voltage. The error voltage is ampl ified and passed through a switchab le low pass fi lter
to generate the control signal for the VCXo. When the phase lock loop is in lock this
control voltage is a dc value. If the phase lock loop is not locked, the control voltage
deviates high and low unti l the phase lock loop locks.
Switchable Low Pass Filter
(020 1 , R2 1 4, C207, C208J
During normal operation the low pass fi lter has a very narrow bandwidth ( = 1 6 Hz). This
bandwidth can change to a wide bandwidth ( = 4 kHz) to allow for a faster phase loop
lock up. When the phase loop is in lock the output of the lock detect subblock is a negative
dc voltage and a FET switch (Q201 ) in the PLL gain and shaping subblock is tu rned off.
I f the phase loop is not in lock the output of the lock detect subblock goes positive turn­
i ng the FET switch on. This switches out the low pass filter and the U N LOCK signal is
sent out to ind icate the phase Iock is unlocked. When the output ofthe lock detect retu rns
to a steady po
s
i t i v
e
voltage, the and low pass fi lter changes
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