C I RC U I T D E SC R I PTIONS
MO D E L 3562A
6-92
KYS E l
KEYBOARD S E L E CT
Active Low
LE D1 L
LE D2L
OREG E N L
O RE G L
PAO to PA7
RPG1
RPG2
The keyboard com mand register uses KY$E L to interrupt the keyboard
processor when the keyboard has been addressed by the system
processor.
LED 1 E NABLE
Active Low
This signal clocks the system data bus through the L E D's I nput
K
egister
into the keyboard L E D's Latch 1 .
LED 2 E NABLE
Active Low
This signal clocks the system data bus through the LE D's I nput Register
into the keyboard L ED's Latch 2.
OUTPUT REG IST E R E NABLE
Active Low
When this signal is low, keyboard data from the data output register
is put on the system bus.
OUT PUT REG I ST E R
Active Low
This signal clocks keyboard data into the data output register.
PORT AO to PORT A7
Port A l i nes are output l ines of the keyboard processor. The keyboard
processor uses PAO to PA6 to set up the key matrix and uses PA7 to
clock I RQT2 L to the A2 System CPU.
ROTAT ION PULSE G E N E RATOR 1
When the marker RPG is moved, T u rn Latch 1 sends RPG1 to the
keyboard processor.
ROTAT I O N PULSE G E N E RATOR 2
. . ..
RP.G js
Tu�n
2
.RP.(:;4
_
" .'
'. ,
.
XL
X C U RSOR
Active Low
YL
Output signal of L E D's Latch 1 . It enables the X c u rsor LED and Turn
Latch 1 .
Y C U RSOR
Active Low
Output signal of L E Ds Latch 1 . It enab les the Y c u rsor LED and T u rn
Latch 1 .
Содержание 3562A
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Страница 149: ...IODEL 3562A R1 0 A22 Board Location Key Figure 3 1 7 Analog source component locator A30R 1 0 ADJUSTMENTS 3 21 3 22 ...
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Страница 207: ...MODEL 3562A CR Cl ...
Страница 209: ...MODE L 3562A Cl ...
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Страница 213: ...r A1 a pQWERSuP PLY I 03562 66518 REV A REV 8 8MPOUT 58 58 FRONT REAR P ANEL ii O N ...
Страница 214: ... C401 8S1 15ISI t 1 J400 ...
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Страница 224: ...A3 CQVLCLI A3 ...
Страница 231: ...S V InO 3J nOS N I l3 3 1 1 1X3 NI 31dWVS lX3 H l 1 3 NNVH I 0 Ioe J ...
Страница 237: ...Sample Clock SAMP DS DATA oe _ _ _ _ _ BUS NOTE FULL SPA BASi BAI MODE ...
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Страница 259: ...WRITEL A22L l cc E Vl 8 MHz A23L ASL Inverting A1L A21 L D rivers r ...
Страница 305: ...c c I O Sequencer S r J Sequence Decoder ...
Страница 311: ... FROM 7 1 A2 SYSTEM CPU Dcf L TO 07L FROM A2 SYSTEM CPU ADDRESS L I N ES 7 1 DTACKL A2 SYSTEM CPU IRQTL ...
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Страница 321: ... From Digital Source From Digital Source Serial Data Serial Data Sinewave Interface Front End Interface 3 S D D ...
Страница 324: ...EXT TRIGGER TRIG 1 TRIG 2 CALTRIG CNTLD COMI W CNTCLK LDTRGL RESETL ...
Страница 327: ... RH r I N EXT BUFFER SAMPLE _ _ _ IN ...
Страница 425: ...L_ FAULT ISOLATION Instrument Operational Figure 7 1 3 SELF TEST Sequence MODEL 3562A STOP Enter failure in r t be 7 61 ...
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