HP 3562A, Руководство по обслуживанию

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C I RC U I T DESCRI PT IONS MO D E L 3S62A
6-50
The
local data/DMA bus interface
(AS U406 and ASU41 1 ) latches start and stop addresses
onto the DMA bus. This information is u sed by the DMA controller(s) to partition the global
RAM on AB for the d ifferent output modes of the DMA contro l le r.
The
global data bus interface
(AS U304 and ASU404 for the channel one digital f i lter and
ASU31 3, AS U41 3 for the channel two d igital f i lter) latches data f rom the digital f i lter data
bu sses to the global data bus.
The
global bus DMA control
circuit takes the decoded address info rmation f rom the DMA
address decod ing fu nctional block. The decoded information programs this block i nto
the correct state machine mode for the output f rom the d igital f i lters. The contro l l ine
outputs f rom this f u n ctional block control the ti ming and synchronization of the output
b uff ers and AB global RAM addressing.
The
parallel input contro l
circuit controls the transfer of parallel data f rom the global
RAM i nto the digital f i lters through the global data bus interf ace.
A6,
Digital Filter Controller Block Descriptions
Refer to f igure 6-ASd, A6 Bl ock Diagram, for the fol lowing circuit block descriptions.
SYSTEM DATA BUS I NTE RFAC E
The system data bus i nterface consists of tristate transceivers connecting the system data
b u s and the local data bus. The system CPU conf igu res and reads status f rom various
registers in the digital f i lter assembly through this interf ace and the local data bus.
SYSTEM ADDRESS DECOD E R
The system add ress decoder i s divided between the AS and A6 boards with some of the
c ircu itry appearing on each . The system address bus is connected to the A6 control board.
Part of the add ress (ASL-AB L and VIOL) is decoded by the system address decoder (A6U404).
T h is IC is an eight-b it identity comparator conf igu red to activate the signal MYA D D RSL
when the f iiter assembiy is add ressed by the system C P U .
decoders on the control (A6) and f i l ter boards A(S).
The add ress decoder on the control board (A6U304) decodes add ress information into
measurement com mands, counting i nstru ctions, and interrupt masks.
DATA PO I NT COUNTER
The data point cou nter mon itors the informati on requ i red to synchronize the actions of
the various components of the fi lter assembly. A6U1 09 contains f ive 1 6-bit cou nters u sed
to cou nt th e nu mber of data points (samp les) stored in G l obal RAM. Conf igu ration
i nformation f rom the system CPU is written into this cou nter and status information read
f rom it via the local data bus. E ach of the f ive cou nters has an output (OUT1 through
OUTS) to signal when the cou nter has reached its term inal cou nt.