HP 3562A, Руководство по обслуживанию

Страница: 295 / 570

C I RC U I T D E SCRI PTIONS MOD E L 3562A
6-76
Address Generation
The FFT board must create addresses for the data input from and output to RAM when
it has control of the global bus. This function is a major portion of the activity on the
FFT board. The block entitled Add ress Generation on the main block diagram has its own
block d iagram made up of the blocks l isted as follows. Refer to figure 6-A9b for the fol low­
i n g discussion.
•
I/O Sequencer
•
Sequence Decoder
•
Cou nters One and Two
•
Add ress Translator
•
Page Register
•
Coefficient ROM
I /O S E Q U E NC E R
The I/O sequencer (U1 1 7) controls the I/O process when the FFT board has control of the
global bus. It manages the timing for global bus I/O and directs the generation of addresses
used to transfer data to and from global RAM. The TMS320 system co ntrols the I/O
sequencer through the hardware control register. The sequencer is synchron ized to the
TMS320 operations through the port decoder to te l l the sequencer when the TMS320 has
accessed or provided data for the next I/O operation. The sequencer also i n itiates hand­
s h aking when the FFT needs memory access.
S E Q U E NC E D ECOD E R
T h e sequence decoder (U1 1 5) decodes the outputs of the I/O sequencer. When the TMS320
begins a new level (the Fast Fourier Transform is performed in "level s", five of which are
cal led "butterfly routines") it initial izes the sequencer by activating LDHWCRL (load hard­
ware control register). This signal from the port decoder also presets the seq uencer (U1 1 7),
starti ng the sequencer process. The memory access process is as fol l ows:
e
The sequencer asserts REQG B L (req uest global bus) to the global bus handshaking
circu itry which produ ces a mem ory request (MRFFTL) to global RAM .
uest is
•
If it's a read operation the read registers get l oaded by G D S L (global data strobe). I f
it's a write operation, the write registers o n the global data b u s are enabled and the
G R/GWL (global read/global write) signal is set low.
•
When global RAM rem oves the memory grant signal (signal ing that the cycle is com­
plete) the address, data, and global write l ines are all deactivated.