HP 3562A, Руководство по обслуживанию

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C I RC U I T D E SCRI PT I ONS
MOD E L 3S62A
6-1 34
DATA1
DATA2
DAV
DAVL
DATA1 , DATA2
(A32, A34 TP61 0)
These two signals are the serial data streams from the A32, A34 Analog
Digital Converters to the AS D igital Filter. Data transfer begins th ree
clock cycles after the assertion of DREQL and occurs at a 1 0.1 4 MHz
rate. The first b it is the data val id bit, fol lowed by the overload status
bits, then the 1 3 bit serial data with the LSB first.
DATA VAL I D
Signal to and from the A 2 System CPU to the A22 H P-I B . T h i s l i ne is
used in the H P-I B handshake sequence.
DATA AVA I LA B L E
Active Low
The AB G lobal RAM sends the A1 7 Display I nterface this control signal
after it writes the data for the HP 1 34SA into the A 17 Display I nterface
registers. The A 1 7 Display I nterface then sends DAVL to the H P 1 34SA
which tel ls the display that data is available. DAVL works with RFDL
(Ready For Data) to transfer data to the HP 1 34SA display. Refer to
the H P 1 34SA service manual section 3-6 for the handshake timing
information.
D I SPLAY OUTPUT
X, Y, Z
;,
DMADTACKL
D R E L
DSA SS
These signals are outputs of the H P 1 34SA d isplay. Refer to the
HP 1 345A operating and service manual for troubleshooting and adjust­
ing the d isplay.
DMA DATA T RA N S F E R ACKNOWLEDG E
Active Low
This signal is from the AS Digital Filter to the A6 Digital Filter Controller.
When a 'read fi lter status' command or a read/write to a AS DMA
controller register is completed, DMADT ACKL goes low. The A6 Digital
Fi lter Controller then sends DTACKL to the A2 System CPU to indicate
the command is completed.
c Ive ow
When the AS D igital Filter is ready for data, it sends the DREQL signal
to the A32, A34 Analog Digital Converters. The d igital filter expects
the data back on the forth clock cycle after the DREQL. This signal
is also sent to the A1 Digital Source. The digital source uses the DREQL
to synchronize the buffer start signal (B FST) go ing to the A6 D igital
Filter Control ler with the sample signal (SAMP) from the A34 Analog
Digital Converter.
DSA START/STO P
(AS TP1 3, A6 T P7)
This signal corresponds to bit 2 of the AS Dig ital F ilter assembly
command register. The AS D igital Filter and the A6 D igital F ilter
Control ler use the DSA SS signal for d i agnostic testi ng.