HP 3562A, Руководство по обслуживанию

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MOD E L 3S62A
C I RC U I T DESC R I PT I O N S
The trigger controller activates TR IGATE L, s igna l i ng the cou nters to conti nue
counting i nput samples, and the measu rement runs to com pletion.
The start/stop controller controls the AS D igital Fi lter outputs. CH1 STOP1 controls
DF1 main output and CH 2STOP1 contro ls DF2 main output.
When a triggered measurement is complete the output of the start/stop contro l ler
(BLKDON E) is sent to the m easurement control state machine.
I NTE RRUPTS
There are six interrupt flags:
TR I G G E R E D
MARK ER
BLOC K3 FULL
BLOCK2 F U LL
BLOCK1 F U L L
I N BLOCKEMPTY
Set if a val id trigger event has occu rred afte r ARML is
activated
Set if a marker count has fin ished d u ring a freeru n
measu rement
Set when the measurement mode data blocks are complete
for both channels
Set when auxi l iary data block 2 is fil led
Set when the fi ltered auxi li ary data block is fil led
Set when the parallel input data blocks have been emptied
When one of these interrupt flags is set, the digital fi lter control ler sends an i nterru pt
(l RQTS L) to the A2 System CPU. After receivi ng the i nterru pt, the system CPU reads the
I nterrupt Register Latch (U302) to determ ine which signal caused the interru pt.
Any combination of fl ags may be cleared through the CLRI NTL signal and the local data
bus. These two signais are AN Ded together into the CLR i nputs of each of the i nterru pt
flag flip-flop registers. Typical ly, the interrupt routine clears only the flag it deals with .
The interrupt mask register (A6 U301) is a write only register that allows selective enabling
of the interru pting events. The correspond ing bit in the mask register must be set to enable
an interrupting event to cause a system i nterru pt.
T R I G G E R L E D CONTROL
This circuit is com posed of a dual monostable mu ltivibrator (A6U31 0) and a one-of-eight
mu ltiplexer (A6U41 0). This circu itry causes the front panel TRIG G E R I N G LED to flash once
each time a trigger is received .
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