HP 3562A, Руководство по обслуживанию

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MODEL 3562A
SWARMl
SWTRIG
TO
T1
T1 0M
TDREQ
TEST
T lODAT
SOFTWARE ARM
Active Low
CIRCUIT DESCRIPTIONS
Signal from the control registers that overrides the software arming of the
phase counters and the buffer start. This signal is used for self-test and
shou ld be high in normal operation.
SOFTWARE TRIGG E R
If SWTRIG is selected with T1 and TO, a trigger occu rs on the low to high
transition of the SWTRIG signal.
TRIGG ER S E lECT
TO and T1 select where the trigger signal will come from.
TO T1 Trigger Sou rce
0 0 A31 Trigger Board (TRIGRO)
0
1 H P-I B Trigger (REMTG L)
1 0 Software Trigger (SWTRIG)
1 1 Source Trigger (BU RSTRIG)
The system CPU may initiate a trigger by setting SWTRIG low, then high.
TEST 10 MHz CLOCK
In the digital source self-test mode this signal becomes the 1 0 MHz clock,
the LO serial data clock, and the serial data shift clock.
DATA REQU E ST
This signal is used when in the self-test mode as the data request line.
TEST
This signal enables the self-test signals to be mu ltiplexed into the data paths
and clock lines. This signal must be low for the assembly to function in
the normal mode.
TEST LOCAL OSC I L LATOR DATA
This signal is used as the LO serial data for the self-test instead of using
LO data.
LOAD
This signal is used in testing the LO input receiver.
TRIG
TRIGGER
When TRIG goes high, the phase state machine strobes the cu rrent count
of the phase cou nters into the counters' output registers.
TRIGGERED
TRIGG ERED
TTH
Signal from the phase resolution circuit to the status registers. When the
ARML signal is received, TRIGG ERED goes low. When a trigger is received,
TRIGG E RE D go high. This indicates the trigger has occu rred.
TEST TRACK/HOLD
In the self-test mode this signal becomes the sample clock.
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