HP 3562A, Руководство по обслуживанию

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C I RC U I T DESCRI PTIONS
MOD E L 3S62A
The AS Digital Fi lter sends the SYNC2 signal to the LO when it is ready for the next sine
and cosine wave data points. The data poi nts are synchronized with SYNC2 and shifted
o u t to the d igital fi lter and digital sou rce. Each serial data stream represents one point
(ampl itud� value) on a sine or cos i n e wave.
E ach sample period corresponds ,to an LO° 'csuper-cycle'. Each super-cycle is com posed
of four cycles defined by the state variables SO and 51 . The phase accum u l ator generates
a p hase value for si ne, cosine, or sou rce d u ring each cyc le except for one which is used
for general housekeeping. This i s shown below:
51 (U 46-5)
o
o
1
so
(U46-9)
o
1
1
SYNC2 occu rs
1
o
Output of Phase Accumulator
Cosine data point
No output, set up for next su per-cycle
S i n e data point
NDAT data po int
While the present phase values are being generated in the phase accumulator, the previous
set of data points are being processed in the i nterpolator and adder, and the set of data
po i nts before that are being sent to the digital filter and d igital source. So, at any given
time, there are a cou ple of sets of data points in process. The process repeats u ntil the
LO operation is changed by the system CPU.
W hen a trigger occu rs, the phase value of the cosine is latched into the phase output
l atchs. The system CPU reads this val ue through the system bus i nterface and uses this
i nformation for an i n put correction factor. The self-test shift registers are u sed to test the
assem bly. During self-test, the system CPU reads and verifie's the val u es from the self-test
s h ift registers and the phase latchs.
System Bus 'nteifaCe
A l l commun ications between
6-40
system bus PAL controls a l l the signals to and
from the system C P U . To send a comm and or data to the LO, the system CPU puts the
command or data on the system data bus (00 to 07) and add resses the LO. A comparator
(U37) checks A4L to A8L, LDSL, ASl, and VIOL for a val id add ress. When the add ress is
val id, the comparator asserts the Val id Add ress l ine (VAOO R) which enab les the system
b u s PAL. The PAL sets the Va lid Peripheral Address line (VPA L) low to enable the system'
d ata bus b uffers (U24, U28) and to handshake with the system C P U . When the system
C P U receives VPAL, it synchronizes the Val id Memory Address l ine (VMAL) with the
E nable Clock (E N BLL). The data is transferred while VMAL is low. System bus l ines are
o n ly val id as long as VMA L is low.