HP 3562A, Руководство по обслуживанию

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MOD E L 3562A C I RC U IT DESCR I PT I O N S
Square Wave Source
The DAC load signal (DACLD) on p i n 36 is used for a number of thi ngs in this part of
the analog sou rce. This 256 kHz squ are wave is divided by U450 (a dual 4-b it cou nter)
which yields squ are waves whose frequencies are 64 kHz and a 4 kHz. Both signals are
connected to the signal selection c i rcu it.
Pseudo Random Source
DACLD clocks U455 (serial sh ift register with 8-bit parallel output) which drives a group
of gates, the end result of which is a pseudo random bit stream which repeats itself every
256 clock cycles. This signal and its i nverse is connected to the signal selection circu it.
Signal Selection
Signal selection is done by U452 (a d ual 1 -of-4 selector/mux) and rec locking is done by
U451 . I nputs to this block consist of two squ are waves (64 kHz and 4 kHz) from U450
and the pseudo random noise (PRN) s ignal and its inverse. The control l i nes S E LCAL and
I NVCAL from U502 select one of the four signals to pass to the cal ibrator circuit and
to send to the trigger board as the s ignal CALT R I G . Pseudo random noise is not used for
a CAL T R I G signal, but a signal from the PRN sou rce is connected to both C2 and C3 of
the CAL TRIG selector, U452A. See tab le A30-2 in section VI I I for specific control
information.
Calibrator
The 6.2 volt reference is d ivided by R5 and R6 such that 0.2 volts appears on the i nverting
i nput of U1 . A feed back loop through Q1 , Q2/Q3, and R7 forces the vol tage across R8
to be the same as across R5. This m akes Q1 a stable cu rrent sou rce for Q2 and Q3. The
bases of this trans istor pair are driven by the TTL signal from the signal selection b lock
such that one of the pair is on and the other is off at any given time. When Q3 is off
there is no voltage drop across R1 6 and R1 0; when Q3 is on there is a voltage drop. S i n ce
the cu rrent through Q2 and Q3 is very we l l regulated, the voltage appearing on its collec­
tor is very stable.
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