Inteli NT MINT, SW Version 2.6, ©ComAp – November 2011
IGS-NT-MINT-2.6-Reference Guide.PDF
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lose /open output controls the generator Neutral circuit breaker. It is intended for
continual active signal if NCB should be closed. See also setpoint
Neutral cont
.
LdShed stage 2
ing outputs for partial load switching.
utputs – Control loops
Neutral CB C/O
Neutral circuit breaker c
contactors – provides a
LdShed stage 1
LdShed stage 3
Load shedd
Binary o
AVR up
AVR dn
for Volt / PF control by motorized or electronic potentiometer.
instead of analog Speed governor
of
are produced
of
eds minimal pulse length, pulse is generated to appropriate
output.
Binary outputs
Speed up
Speed dn
Bina o
used
ry utputs for Synchronizing and Load control. Outputs can be
output for older engine types. Minimum pulse duration is 0,15 sec. Maximum pulse duration is 10,0 sec.
Binary outputs UP nad DOWN of a PID regulator produce pulses, whose length correspond to derivation
the analog output (further AOUT) of the same regulator. In other words:
1. If there is no change of the AOUT, no pulses
2. If the AOUT is increasing, pulses are generated on the UP output. Pulse length depends on speed
the increase.
3. If the AOUT is decreasing, pulses are generated on the DOWN output. Pulse length depends on
speed of the decrease.
4. Long pulses on the same output can merge
5. If the calculated pulse in each particular cycle is too short, it is not copied to the output, but is only
buffered. When the buffered pulse exce
The pulses are generated even if the analog regulator output is already at limit value. As for speed and
voltage regulation, this kind of regulation is good for droop-based systems. At isochronous system, it can
cause stability problems, because it is slower.
Hint:
When Speed governor output stays near to the limit value (
SpeedGovLowLim
+0,2 V or
SpeedGovHiLim
-0,2
V) for more than 2 sec, the “Wrn SpdRegLim” message is displayed in the Alarm list and recorded to History.
When AVRi output stays on <2% or >98% for more than 2 sec, the “Wrn VoltRegLim” is displayed in the
Alarm list and recorded to History.
Corresponding warning is blocked when Binary outputs Speed Up, Speed Dn or AVR up, AVR dn are
configured to a physical BO or VPIO.
It is not recommended to process these signals via the internal PLC, as the precise signal timing would be
distorted.
