SPI General Operation
10-32
ADSP-BF535 Blackfin Processor Hardware Reference
The
SCK
signal is used to shift out and shift in the data driven onto the
MISO
and
MOSI
lines. The data is always shifted out on one edge of the
clock (the
active edge
) and sampled on the opposite edge of the clock
(the
sampling edge
). Clock polarity and clock phase relative to data are pro-
grammable into
SPIx_CTL
and define the transfer format.
Master Mode Operation
When the SPI is configured as a master (and DMA mode is not selected),
the interface operates in the following manner.
• The core writes to
SPIx_FLG
, setting one or more of the SPI flag
select bits (
FLSx
). This ensures that the desired slaves are properly
deselected while the master is configured.
• The core writes to the
SPIx_CTL
and
SPIx_BAUD
registers, enabling
the device as a master and configuring the SPI system by specifying
the appropriate word length, transfer format, baud rate, and other
necessary information.
• If
CPHA = 1
, the core activates the desired slaves by clearing one or
more of the SPI flag bits (
FLGx
) of
SPIx_FLG
.
• The
TIMOD
bits in
SPIx_CTL
determine the SPI transfer initiate
mode. The transfer on the SPI link begins upon either a data write
by the core to the transmit data buffer
(SPIx_TDBR
) or a data read
of the receive data buffer (
SPIx_RDBR
).
• The SPI then generates the programmed clock pulses on
SCK
and
simultaneously shifts data out of
MOSI
and shifts data in from
MISO
.
Before a shift, the shift register is loaded with the contents of the
SPIx_TDBR
register. At the end of the transfer, the contents of the
shift register are loaded into
SPIx_RDBR
.
• With each new transfer initiate command, the SPI continues to
send and receive words, according to the SPI transfer initiate mode.
Содержание ADSP-BF535 Blackfin
Страница 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...
Страница 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 908: ...SDRAM Controller External Bus Interface Unit B 36 ADSP BF535 Blackfin Processor Hardware Reference...