ADSP-BF535 Blackfin Processor Hardware Reference
3-17
Operating Modes and States
When the
BMODE
pins are set to b#000 and the No Boot on Software Reset
bit is set, the core begins fetching instructions from address 0x2000 0000
(the beginning of ASYNC Bank 0).
Core Only Software Reset
A software reset is initiated by executing the
RAISE 1
instruction or by set-
ting the Software Reset (
SYSRST
) bit in the core Debug Control register
(
DBGCTL
) via emulation software through the JTAG port. (
DBGCTL
is not
visible to the memory map).
A Core Only Software reset affects only the state of the core. Note the sys-
tem resources may be in an undetermined or even unreliable state,
depending on the system activity during the reset period.
Booting Methods
The internal boot ROM includes a small boot kernel that can either be
bypassed or used to load user code from an external memory device, as
defined in
Table 4-10 on page 4-37
. The boot kernel reads the
BMODE[2:0]
pin state at reset to identify the download source (see
Table 4-7 on page 4-22
). When in Bypass mode, the processor is set to
execute from 16-bit wide external memory at address 0x2000 0000
(ASYNC Bank 0).
Several boot methods are available in which user code can be loaded from
an external memory device. For these modes, the boot kernel sets up the
selected peripheral based on the
BMODE[0:2]
pin settings.
For each boot mode, user code read in from the memory device is placed
at the starting location of L2 memory (0xF000 0000). The boot kernel
terminates the boot process with a jump to the start of the L2 memory
space. The processor then begins execution from this address.
Содержание ADSP-BF535 Blackfin
Страница 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...
Страница 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...
Страница 908: ...SDRAM Controller External Bus Interface Unit B 36 ADSP BF535 Blackfin Processor Hardware Reference...