Altera Stratix II GX, Руководство пользователя

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Altera Corporation 2–31
October 2007 Stratix II GX Device Handbook, Volume 2
Stratix II GX Transceiver Architecture Overview
the clocks from the central block of the master transceiver. The individual
channel clock distribution of the slave transceiver is the same as the
master transceiver.
Figure 2–21. Receiver Channel PIPE ×4 and × 8 Modes
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer ( Figure 2–22 ) is located
at the device’s logic array interface in the transmitter block and
compensates for phase difference between the transmitter clock and the
clock from the PLD. The transmitter phase compensation FIFO buffer
operates in two modes: low latency and high latency. In the low latency
mode, the FIFO buffer is four words deep. The Quartus II software
chooses low latency mode automatically for every mode except the
PCI-Express PIPE mode (which automatically uses high latency mode). In
high latency mode, the FIFO buffer is eight words deep.
Figure 2–22. Transmitter Phase Compensation FIFO Buffer
The phase compensation FIFO buffer’s read port is clocked by the
transmitter PLL clock. The write clock is fed by
tx_clkout
of the
associated channel in a single-channel configuration. The FIFO buffer’s
write clock is clocked by
coreclkout
in the four- or eight-channel
configuration.
Receiver Digital Logic
Receiver Analog Circuits
RX Phase
Compen-
sation
FIFO
Clock
Recovery
Unit
Word
Aligner
8B/10B
Decoder
Byte
De-
serializer
Byte
Ordering
PIPE
Rate
Match
FIFO
De-
serializer
PLD
coreclkout
XCVR
Central Block Reference
Clocks
÷
1, 2
Transmitter
Phase Compensation
FIFO
dataout[39..0]
From PIPE
or PLD
datain[39..0]
Control Signals in [3..0 Control Signals out [3..0]
To Byte Serializer
tx_clkout or
coreclk_out
From PLD
Slow-Speed
Transmitter Clock