Altera Stratix II GX, Руководство пользователя

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2–30 Altera Corporation
Stratix II GX Device Handbook, Volume 2 October 2007
Transmitter Modules
the slow-speed clock from the master transceiver. The PIPE interface and
the write port of the transmitter phase compensation FIFO buffer is
clocked by the
coreclkout
signal of the master transceiver. The slave
transceiver does not output a
coreclkout
signal because the CMU is
powered down.
Figure 2–19. Transmitter Channel Clocking in Transceiver Mode
For the receiver logic, in XAUI mode ( Figure 2–20 ), the local recovered
clock feeds the logic up to the write clock of the deskew FIFO buffer. The
recovered clock from
channel[0]
feeds the read clock of the deskew
FIFO buffer and the write port of the rate matcher. The slow clock from
the central block feeds the rest of the logic up to the write port of the phase
compensation FIFO buffer. The
coreclkout
signal routed through the
PLD from the central block feeds the read side of the phase compensation
FIFO buffer.
Figure 2–20. Receiver Channel Clocking in XAUI Mode
In the PIPE ×4 and PIPE ×8 modes ( Figure 2–21 ), the local recovered clock
feeds the logic up to the write port of the rate matcher FIFO buffer. The
slow clock from the central block feeds the rest of the logic up to the write
port of the phase compensation FIFO buffer. The
coreclkout
signal
routed through the PLD from the central block feeds the read side of the
phase compensation FIFO buffer. In PIPE ×8, the slave transceiver takes
Byte
Serializer
Transmitter Analog Circuits
Transmitter
Digital
Logic
Serializer
PLD
Logic
Array
Phase
Compen-
FIFO
sation
TX
8B/10B
Encoder
PIPE
Interface
XCVR
Central Block Reference
Clocks
coreclkout
÷
1, 2
Receiver Digital Logic
Receiver Analog Circuits
RX Phase
Compen-
sation
FIFO
Clock
Recovery
Unit
Word
Aligner
8B/10B
Decoder
Byte
De-
serializer
Byte
Ordering
Rate
Match
FIFO
Deskew
FIFO
De-
serializer
PLD
coreclkout
XCVR
Central Block Reference
Clocks
Recovered Clock
from Channel 0
÷
1, 2