Altera Stratix II GX, Руководство пользователя

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3–88 Altera Corporation
Stratix II GX Device Handbook, Volume 2 October 2007
Channel and Clock Multiplier Unit (CMU) PLL Reconfiguration
Figure 3–38 shows the transceiver blocks (grayed out) that can be
dynamically reconfigured using the channel reconfiguration feature.
1
Figure 3–38 shows that the TX PLLs and the clock multiplexer
on the transmit side (inside the clock multiplier unit) could not
be reconfigured using these features. It also shows that only two
sources of input reference clocks were available for the TX PLLs
and RX PLLs.
Figure 3–38. Reconfigured Functional Blocks with Channel Reconfiguration Note (1)
Note to Figure 3–38 :
(1) Supported from the Quartus II software version 6.1.
Overview of Quartus II Software Version 7.1 Features for
Dynamic Reconfiguration
The Quartus II software version 7.1 provides the following enhancements
to support dynamic reconfiguration:
■
Three additional features to dynamically reconfigure the transceiver
channel and the TX PLLs:
●
TX PLL-only reconfiguration
●
Channel and TX PLL reconfiguration
●
Channel reconfiguration with TX PLL select
■
The number of possible clock sources for the input reference clocks is
increased from two to five.
clock
MUX Main
TXPLL
Clock Multiplier Unit
Full Duplex Transceiver Channel
TX CHANNEL
Logical
TX PLL
Select
LOCAL
DIVIDERS
d analog logic
clock
MUX
RX CHANNEL
clock
MUX
d analog logic
RX PLL
clock 1
clock 0
Main
TXPLL