Altera Stratix II GX, Руководство пользователя

Страница: 350 / 672

3–102 Altera Corporation
Stratix II GX Device Handbook, Volume 2 October 2007
Channel and Clock Multiplier Unit (CMU) PLL Reconfiguration
Figure 3–47 shows the functional blocks that are reconfigured after the
dynamic reconfig controller writes the mode2 MIF. Note that on the
receive side, the rate matcher gets enabled after reconfiguration since the
mode2 MIF contains settings to enable the rate matcher block.
Figure 3–47. Reconfigured Functional Blocks After the Channel and TX PLL Reconfiguration
TX PLL Reconfiguration
Using the TX PLL reconfiguration mode, you can reconfigure the
TX PLLs. This mode is very useful in saving reconfiguration time in
certain applications. Consider that you have four transmit-only instances
in the same transceiver block that switch to different data rates together
(assuming that the functional blocks are the same across the data rates).
In this case, all these channels can listen to the same TX PLL. Instead of
using the
Channel and TX PLL Reconfiguration option (write 38 words)
for individual channels, you can configure the TX PLL (write 10 words)
once, to a different data rate. This, in turn, changes the transmit data rate
of all the channels listening to this TX PLL.
This mode is also useful when combined with the channel
reconfiguration with TX PLL select mode. When the channel is listening
to one TX PLL, you can reconfigure the other TX PLL, and later switch the
transmit channel to listen to the configured TX PLL (explained in
“Channel Reconfiguration with TX PLL Select” on page 3–103 ).
/1
pll_inclk_rx_cruclk[1]
156.25 MHz
pll_inclk_rx_cruclk[0]
125 MHz
Clock Multiplier Unit
clock
MUX
clock
MUX
6.25 Gbps
LOGICAL
TXPLL0
2.5 Gbps
LOGICAL
TXPLL1
Reconfigured functional blocks after MIF write
Rate Matcher Enabled
RX CHANNEL
6.25 Gbps
RX PLL
clock
MUX
6.25 Gbps
d analog logic
6.25 Gbps
d analog logic
Full Duplex Transceiver Channel
TX CHANNEL
Logical
TX PLL
Select
LOCAL
DIVIDER