Altera Stratix II GX, Руководство пользователя

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Altera Corporation 2–33
October 2007 Stratix II GX Device Handbook, Volume 2
Stratix II GX Transceiver Architecture Overview
The byte serializer takes in a 40-, 32-, 20-, or 16-bit-wide input from the
phase compensation FIFO buffer and serializes it to 20, 16, 10, or 8 bits,
respectively (refer to
Table 2–7 ). At the same time, the clock frequency is
doubled.
After serialization, the byte serializer transmits the least significant byte
to the most significant byte. Always use the transmitter digital reset to
reset the byte serializer FIFO pointers whenever the transmitter PLL loses
lock. Refer to
“Reset Control and Power Down” on page 2–214 for further
details on the reset sequence.
Figure 2–24 shows byte serializer input and output signals when
serializing a 20-bit input to 10 bits. The
tx_datain
signal is the input
from the FPGA’s logic array that has already passed through the
transmitter phase compensation FIFO buffer.
Figure 2–24. Transmitter Byte Serializer
In Figure 2–24 , the LSB is transmitted before the MSB in the transmitter
byte serializer. For the input of D1, the output is D1
LSB
and then D1
MSB
.
8B/10B Encoder
The 8B/10B encoder (refer to Figure 2–25 ) is part of the Stratix II GX
transceiver digital blocks and lies between the byte serializer and the
serializer. The 8B/10B encoder operates in two modes: single-width and
double-width and can be bypassed if the 8B/10B encoder is not used. In
single-width mode, the 8B/10B encoder generates a 10-bit code group
Table 2–7. Byte Serializer Input and Output Data Widths
Input Data Width
(Bits)
Output Data Width After Byte Serialization
(Bits)
40 20
32 16
20 10
16 8
D1
LSB
D1
MSB
D2
LSB
D2
MSB
datain[19..0]
dataout[9..0]
D1 D2 D3
{10'h3E0, 10'h2A0}
xxxxxxxxxx 10'h2A0 xxxxxxxxxx 10'h3E0 10'h318 10'h3C7
{10'h318, 10'h3C7} {10'h2AA, 10'h333}