Multiply-accumulate unit (MAC)
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the interrupt routine, MRW must be saved by the user and restored before the end of the
interrupt routine.
Note:
The Repeat Count should be used with caution. In this case MR should be written as 0. In
general MR should not be set by the user otherwise correct instruction processing cannot be
guaranteed.
4.2.11 MAC
interrupt
The MAC can generate an interrupt according to the value of the status flags C (carry), SV
(overflow), E (extension) or SL (limit) of the MSW register. The MAC interrupt is globally
enabled when the MIE flag in MCW is set. When it is enabled, the flags C, SV, E or SL can
trigger a MAC interrupt whenever they are set, provided that the corresponding mask flag
CM, VM, EM or LM in MCW is also set. A MAC interrupt request sets the MIR flag in MSW:
this flag must be reset by the user during the interrupt routine, otherwise the interrupt
processing restarts when returning from the interrupt routine.
The MAC interrupt is implemented as a Class B hardware trap (trap number Ah - trap
priority I). The associated Trap Flag in the TFR register is MACTRP, bit #6 of the TFR
(remember that this flag must also be reset by the user in case of a MAC interrupt request).
As the MAC status flags are updated (or eventually written by software) during the Execute
stage of the pipeline, the response time of a MAC interrupt request is three instruction
cycles (see
). It is the number of instruction cycles required between the time the
request is sent and the time the first instruction located at the interrupt vector location enters
the pipeline. Note that the IP value stacked after a MAC interrupt does not point to the
instruction that triggers the interrupt.
Figure 18. Pipeline diagram for MAC interrupt response time
4.2.12
Number representation & rounding
The MAC supports the 2’s-complement representation of binary numbers. In this format, the
sign bit is the MSB of the binary word. This is set to zero for positive numbers and set to one
for negative numbers. Unsigned numbers are supported only by multiply/multiply-
accumulate instructions which specifies whether each operand is signed or unsigned.
In 2’s complement fractional format, the N-bit operand is represented using the 1.[N-1]
format (1 signed bit, N-1 fractional bits). Such a format can represent numbers between -1
and +1-2
-[N-1]
. This format is supported when MP of MCW is set.
N
N
N
I1
I1
N
N+2
N+1
N-1
N-1
N-2
N-3
N+1
N-1
N-2
N+4
TRAP (1)
N+2
N+1
TRAP (1)
N+2
I2
TRAP (2)
TRAP (1)
N+3
N+2
N+1
FETCH
DECODE
EXECUTE
WRITEBACK
MAC Interrupt Request
Response Time
TRAP (2)