XBUS asynchronous / synchronous serial interface
UM0404
DocID13284 Rev 2
Pin TXD1/P8.7 must be configured for alternate data output, P8.7 = ‘1’ and DP8.7 = ‘1’, in
order to provide the shift clock. Pin RXD1/P8.6 must be configured as alternate data input
(DP8.6 = ‘0’).
Synchronous reception is stopped by clearing bit S1REN. A currently received byte is
completed including the generation of the receive interrupt request and an error interrupt
request, if appropriate. Writing to the transmit buffer register while a reception is in progress
has no effect on reception and will not start a transmission.
If a previously received byte has not been read out of the receive buffer register at the time
the reception of the next byte is complete, both the error interrupt request flag and the
overrun error status flag S1OE will be set, if the overrun check has been enabled by
S1OEN.
11.3 Hardware
error
detection
To improve the safety of serial data exchange, the serial channel XASC provides an error
interrupt request flag, which indicates the presence of an error, and three (selectable) error
status flags in register XS1CON, which indicate which error has been detected during
reception. Upon completion of a reception, the error interrupt request flag will be set
simultaneously with the receive interrupt request flag, if one or more of the following
conditions are met:
•
If the framing error detection enable bit S1FEN is set and any of the expected stop bit is
not high, the framing error flag S1FE is set, indicating that the error interrupt request is
due to a framing error (Asynchronous mode only).
•
If the parity error detection enable bit S1PEN is set in parity bit receive modes, and the
parity check on the received data bit proves false, the parity error flag S1PE is set,
indicating that the error interrupt request is due to a parity error (Asynchronous mode
only).
•
If the overrun error detection enable bit S1OEN is set and the last character received
was not read out of the receive buffer by software or PEC transfer at the time the
reception of a new frame is complete, the overrun error flag S1OE is set indicating that
the error interrupt request is due to an overrun error (Asynchronous and synchronous
mode).
11.4
XASC baud rate generation
The serial channel XASC has its own dedicated 13-bit Baud rate generator with 13-bit
reload capability, allowing Baud rate generation independent of the GPT timers. The Baud
rate generator is clocked by f
CPU
/ 2. The timer is counting downwards and can be started or
stopped through the Baud rate Generator Run bit S1R in register XS1CON. Each underflow
of the timer provides one clock pulse to the serial channel. The timer is reloaded with the
value stored in its 13-bit reload register each time it underflows. The resulting clock is again
divided according to the operating mode and controlled by the Baud rate Selection bit
S1BRS. If S1BRS = ‘1’, the clock signal is additionally divided to 2/3rd of its frequency (see
formulas and table). So the Baud rate of XASC is determined by the CPU clock, the reload
value, the value of S1BRS and the operating mode (asynchronous or synchronous).
Register XS1BG is the dual-function Baud rate Generator/Reload register. Reading XS1BG
returns the content of the timer (bit 15...13 return zero), while writing to XS1BG always
updates the reload register (bit 15...13 are insignificant).