ST ST10F276E, User Manual, Page: 65 / 564

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UM0404 The central processing unit (CPU)
3.4.2 X-Peripherals control register (XPERCON)
XPERCON (F024h / 12h) ESFR Reset Value: - 005h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- - - - -
XMISC
EN
XI2C
EN
XSSC
EN
XASC
EN
XPWM
EN
XFLAS
HEN
XRTC
EN
XRAM2
EN
XRAM1
EN
CAN2
EN
CAN1
EN
RW RW RW RW RW RW RW RW RW RW RW
Bit Function
CAN1EN
CAN1 Enable Bit
‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled (P4.5
and P4.6 pins can be used as general purpose IOs, but address range 00’EF00h-
00’EFFFh is directed to external memory only if CAN2EN, XRTCEN, XASCEN,
XSSCEN, XI2CEN, XPWMEN an XMISCEN are ‘0’ also).
‘1’: The on-chip CAN1 XPeripheral is enabled and can be accessed.
CAN2EN
CAN2 Enable Bit
‘0’: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled (P4.4
and P4.7 pins can be used as general purpose IOs, but address range 00’EE00h-
00’EEFFh is directed to external memory only if CAN1EN, XRTCEN, XASCEN,
XSSCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also).
‘1’: The on-chip CAN2 XPeripheral is enabled and can be accessed.
XRAM1EN
XRAM1 Enable Bit
‘0’: Accesses to the on-chip 2 Kbyte XRAM are disabled. Address range 00’EE00h-
00’EEFFh is directed to external memory.
‘1’: The on-chip 2 Kbyte XRAM is enabled and can be accessed.
XRAM2EN
XRAM2 Enable Bit
‘0’: Accesses to the on-chip 64 Kbyte XRAM are disabled, external access performed.
Address range 0F’0000h-0F’FFFFh is directed to external memory only if XFLASHEN
is ‘0’ also.
‘1’: The on-chip 64 Kbyte XRAM is enabled and can be accessed.
XRTCEN
RTC Enable
‘0’: Accesses to the on-chip RTC module are disabled, external access performed.
Address range 00’ED00h-00’EDFF is directed to external memory only if CAN1EN,
CAN2EN, XASCEN, XSSCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also.
‘1’: The on-chip RTC module is enabled and can be accessed.
XPWMEN
XPWM Enable
‘0’: Accesses to the on-chip XPWM module are disabled, external access performed.
Address range 00’EC00h-00’ECFF is directed to external memory only if CAN1EN,
CAN2EN, XASCEN, XSSCEN, XI2CEN, XRTCEN and XMISCEN are ‘0’ also.
‘1’: The on-chip XPWM module is enabled and can be accessed.
XFLASHEN
XFlash Enable Bit
‘0’: Accesses to the on-chip XFlash and Flash control registers are disabled, external
access performed. Address range 09’0000h-0E’FFFFh is directed to external memory
only if XRAM2EN is ‘0’ also.
‘1’: The on-chip XFlash is enabled and can be accessed.