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UM0404
The general purpose timer units
9
The general purpose timer units
The general purpose timer units GPT1 and GPT2 are flexible multifunctional timer
structures which may be used for timing, event counting, pulse width measurement, pulse
generation, frequency multiplication, and other purposes. They incorporate five 16-bit timers
that are grouped into the two timer blocks GPT1 and GPT2.
Block GPT1 contains 3 timers/counters with a maximum resolution of 8 CPU clock cycles,
while block GPT2 contains 2 timers/counters with a maximum resolution of 4 CPU clock
cycles and a 16-bit Capture/Reload register (CAPREL). Each timer in each block may
operate independently in a number of different modes such as gated timer or counter mode,
or may be concatenated with another timer of the same block.
The auxiliary timers of GPT1 may optionally be configured as reload or as capture registers
for the core timer. In the GPT2 block, the additional CAPREL register supports capture and
reload operation with extended functionality, and its core timer T6 may be concatenated with
timers of the CAPCOM units (T0, T1, T7 and T8). Each block has alternate input/output
functions and specific interrupts associated with it.
9.1
Timer block GPT1
From a programmer's point of view, the GPT1 block is composed of a set of SFRs. Those
portions of port and direction registers which are used for alternate functions by the GPT1
block are named by ‘Y’ in
All three timers of block GPT1 (T2, T3, T4) can run in three basic modes: Timer, gated timer,
and counter mode, and all timers can count either up or down. Each timer has an associated
alternate input function pin on Port3, which serves as the gate control in gated timer mode,
or as the count input in counter mode. The count direction (Up / Down) can be programmed
by software or can be dynamically altered by a signal at an external control-input pin. Each
overflow/underflow of core timer T3 can be indicated on an alternate output function pin.
The auxiliary timers T2 and T4 can, additionally, be concatenated with the core timer, or
used as capture or reload registers for the core timer.
In incremental interface mode, the GPT1 timers (T2, T3, T4) can be directly connected to
the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD.
Direction and count signals are internally derived from these two input signals - so the
contents of the respective timer Tx corresponds to the sensor position. The third position
sensor signal TOP0 can be connected to an interrupt input.
The current contents of each timer can be read or modified by the CPU by accessing the
corresponding timer registers T2, T3, or T4 located in the non bit-addressable SFR space.
When any of the timer registers is written to by the CPU in the state immediately before a
timer increment, decrement, reload, or capture, the CPU write operation has priority. This is
to guarantee correct results.