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UM0404 System reset
23.9 Reset summary
A summary of the different reset events is reported in the table below.
Table 64. Reset events summary
Event
RPD
EA
Bidir
Sy
nch
.
as
ync
h
.
RSTIN WDTCON flags
min max
PONR
LH
W
R
SHWR
SWR
WD
T
R
Power-on reset
0 0 N Asynch.
1 ms (VREG)
1.2 ms (Reson. + PLL)
10.2 ms (C
PLL)
- 1 1 1 1 0
0 1 N Asynch. 1ms (VREG) - 1 1 1 1 0
1 x x Forbidden
x x Y Not applicable
Hardware reset
(asynchronous)
0 0 N Asynch. 500ns - 0 1 1 1 0
0 1 N Asynch. 500ns - 0 1 1 1 0
0 0 Y Asynch. 500ns - 0 1 1 1 0
0 1 Y Asynch. 500ns - 0 1 1 1 0
Short hardware
reset
(synchronous)
(1)
1 0 N Synch.
max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
0 0 1 1 0
1 1 N Synch.
max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
0 0 1 1 0
1 0 Y Synch.
max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
0 0 1 1 0
Activated by internal logic for 1024 TCL
1 1 Y Synch.
max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
0 0 1 1 0
Activated by internal logic for 1024 TCL
Long hardware
reset
(synchronous)
1 0 N Synch.
1032 + 12 TCL +
max(4 TCL, 500ns)
-
0 1 1 1 0
1 1 N Synch.
1032 + 12 TCL +
max(4 TCL, 500ns)
-
0 1 1 1 0
1 0 Y Synch.
1032 + 12 TCL +
max(4 TCL, 500ns)
-
0 1 1 1 0
Activated by internal logic only for 1024 TCL
1 1 Y Synch.
1032 + 12 TCL +
max(4 TCL, 500ns)
-
0 1 1 1 0
Activated by internal logic only for 1024 TCL