DocID13284 Rev 2
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UM0404
CAN modules
Note:
The busoff recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by
setting or resetting bit
Init
. If the device goes busoff, it will set bit
Init
of its own accord,
stopping all bus activities. Once bit
Init
has been cleared by the CPU, the device will then
wait for 129 occurrences of Bus Idle (129 * 11 consecutive recessive bits) before resuming
normal operations. At the end of the busoff recovery sequence, the Error Management
Counters will be reset.
During the waiting time after the resetting of bit
Init
, each time a sequence of 11
recessive
bits has been monitored, a
Bit0Error
code is written to the Status Register, enabling the
CPU to readily check up whether the CAN bus is stuck at
dominant
or continuously
disturbed and to monitor the proceeding of the busoff recovery sequence.
Status Register
CAN1SR (EF02h)
XBUS
Reset Value: 0000h
CAN2SR (EE02h)
XBUS
Reset Value: 0000h
EIE
Error Interrupt Enable
‘0’: Disabled - No Error Status Interrupt will be generated.
‘1’: Enabled - A change in the bits
BOff
or
EWarn
in the Status Register will
generate an interrupt.
DAR
Disable Automatic Retransmission
‘0’: Automatic Retransmission of disturbed messages enabled.
‘1’: Automatic Retransmission disabled.
CCE
Configuration Change Enable
‘0’: The CPU has no write access to the Bit Timing Register.
‘1’: The CPU has write access to the Bit Timing Register (while
Init
=
one
).
Test
Test Mode enable
‘0’: Normal Operation.
‘1’: Test mode.
Bit
Function
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
BOff
EWarn EPass RxOk
TxOk
LEC
R
R
R
RW
RW
RW