DocID13284 Rev 2
237/564
UM0404
The general purpose timer units
Refer to the device datasheet for a table of timer input frequencies, resolution and periods
for the range of pre-scaler options.
Timer 6 in gated mode
Gated timer mode for the core timer T6 is selected by setting bit-field T6M in register
T6CON to ‘010b’ or ‘011b’. Bit T6M.0 (T6CON.3) selects the active level of the gate input. In
gated timer mode the same options for the input frequency as for the timer mode are
available. However, the input clock to the timer in this mode is gated by the external input
pin T6IN (Timer T6 External Input), which is an alternate function of P5.12 (see
). If
T6M.0 = ‘0’, the timer is enabled when T6IN shows a low level. A high level at this pin stops
the timer. If T6M.0 = ‘1’, pin T6IN must have a high level in order to enable the timer. In
addition, the timer can be turned on or off by software using bit T6R. The timer will only run,
if T6R = ‘1’ and the gate is active. It will stop, if either T6R = ‘0’ or the gate is inactive.
Note:
A transition of the gate signal at pin T6IN does not cause an interrupt request.
Timer 6 in counter mode
Counter mode for the core timer T6 is selected by setting bit-field T6M in register T6CON to
‘001b’. In counter mode timer T6 is clocked by a transition at the external input pin T6IN,
which is an alternate function of P5.12. The event causing an increment or decrement of the
timer can be a positive, a negative, or both a positive and a negative transition at this pin.
Bit-field T6I in control register T6CON selects the triggering transition (see
Figure 92. Block diagram of core timer T6 in gated timer mode
Table 39. GPT2 timer resolution
Timer input selection T5I / T6I
000b
001b
010b
011b
100b
101b
110b
111b
Pre-scaler factor
4
8
16
32
64
128
256
512
Resolution in CPU clock
cycles
4
8
16
32
64
128
256
512
X
T6l
CPU
Clock
T6R
MUX
T6UDE
Core Timer T6
T6IR
Interrupt
Request
T6OTL
T6OE
T6OUT
Up/Down
XOR
1
0
T6UD
T6EUD
T6M
T6IN
P5.12
P5.10
P3.1
Gate
Control