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UM0404
The capture / compare units
The reload registers TxREL are not bit-addressable.
16.2
CAPCOM unit timer interrupts
Upon a timer overflow the corresponding timer interrupt request flag TxIR for the respective
timer will be set. This flag can be used to generate an interrupt or trigger a PEC service
request, when enabled by the respective interrupt enable bit TxIE.
Each timer has its own bit-addressable interrupt control register (TxIC) and its own interrupt
vector (TxINT). The organization of the interrupt control registers TxIC is identical with the
other interrupt control registers.
T0IC (FF9Ch / CEh)
SFR
Reset Value: - - 00h
T1IC (FF9Eh / CFh)
SFR
Reset Value: - - 00h
T7IC (F17Ah / BEh)
ESFR
Reset Value: - - 00h
T8IC (F17Ch / BFh)
ESFR
Reset Value: - - 00h
Note:
Section 5.1.3: Interrupt control registers on page 100
for an explanation of the
control fields.
16.3
Capture / compare registers
The 16-bit capture / compare registers CC0 through CC31 are used as data registers for
capture or compare operations with respect to timers T0 / T1 and T7 / T8. The capture /
compare registers are not bit-addressable.
Each of the registers CC0...CC31 may be individually programmed for capture mode or one
of four different compare modes (except for CC24...CC27), and may be allocated
individually to one of the two timers of the respective CAPCOM unit (T0 or T1, and T7 or T8,
respectively). A special combination of compare modes additionally allows the
implementation of a 'double-register' compare mode.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
T0IR T0IE
ILVL
GLVL
RW
RW
RW
RW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
T1IR T1IE
ILVL
GLVL
RW
RW
RW
RW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
T7IR T7IE
ILVL
GLVL
RW
RW
RW
RW
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
T8IR T8IE
ILVL
GLVL
RW
RW
RW
RW